公开(公告)号：US08296519B2

公开(公告)日：2012-10-23

申请号：US12650961

申请日：2009-12-31

申请人： Guy L. Guthríe ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthríe ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834

摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.

公开(公告)号：US08254411B2

公开(公告)日：2012-08-28

申请号：US11055399

申请日：2005-02-10

申请人： Leo J. Clark ,  Guy L. Guthrie ,  William J. Starke

发明人： Leo J. Clark ,  Guy L. Guthrie ,  William J. Starke

IPC分类号： H04J3/16 ,  H04J3/22 ,  G06F13/00 ,  G06F15/173

CPC分类号： H04L47/722 ,  H04L47/70 ,  H04L49/109

摘要： A data processing system includes a plurality of local hubs each coupled to a remote hub by a respective one a plurality of point-to-point communication links. Each of the plurality of local hubs queues requests for access to memory blocks for transmission on a respective one of the point-to-point communication links to a shared resource in the remote hub. Each of the plurality of local hubs transmits requests to the remote hub utilizing only a fractional portion of a bandwidth of its respective point-to-point communication link. The fractional portion that is utilized is determined by an allocation policy based at least in part upon a number of the plurality of local hubs and a number of processing units represented by each of the plurality of local hubs. The allocation policy prevents overruns of the shared resource.

摘要翻译： 数据处理系统包括多个本地集线器，每个集线器通过相应的一个多个点对点通信链路耦合到远程集线器。 多个本地集线器中的每一个排队对存储器块进行访问的请求，用于在到远程集线器中的共享资源的点对点通信链路中的相应一个上传输。 多个本地集线器中的每一个仅利用其相应点对点通信链路的带宽的小数部分向远程集线器发送请求。 所使用的分数部分由至少部分地基于多个本地集线器的数量和由多个本地集线器中的每一个表示的多个处理单元的分配策略确定。 分配策略可以防止超出共享资源。

公开(公告)号：US20120198167A1

公开(公告)日：2012-08-02

申请号：US13445080

申请日：2012-04-12

申请人： Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834

摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.

摘要翻译： 处理单元包括具有确定存在或不存在预留的预约逻辑的存储下位缓存和包括存储通过上级缓存，指令执行单元，负载单元的处理器核心，该负载单元响应于 由指令执行单元通过执行装载预约指令而产生的加载备用操作的上级缓存暂时缓冲加载备用操作的加载目标地址，以及指示载入预约操作被绑定到 上级缓存中的值。 如果接收到与加载保留操作的加载目标地址冲突的存储修改操作，则处理器核心将该标志设置为特定状态，并且响应于执行存储条件指令，发送关联的存储 - 如果该标志被设置为特定状态，则向低级缓存进行条件操作，并显示故障指示。

公开(公告)号：US20120179876A1

公开(公告)日：2012-07-12

申请号：US12985590

申请日：2011-01-06

申请人： Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0837 ,  G06F12/0895

摘要： A method of processing store requests in a data processing system includes enqueuing a store request in a store queue of a cache memory of the data processing system. The store request identifies a target memory block by a target address and specifies store data. While the store request and a barrier request older than the store request are enqueued in the store queue, a read-claim machine of the cache memory is dispatched to acquire coherence ownership of target memory block of the store request. After coherence ownership of the target memory block is acquired and the barrier request has been retired from the store queue, a cache array of the cache memory is updated with the store data.

摘要翻译： 在数据处理系统中处理存储请求的方法包括在数据处理系统的高速缓存存储器的存储队列中引入存储请求。 存储请求通过目标地址识别目标存储器块并指定存储数据。 当存储请求和存储请求之前的屏障请求在存储队列中排队时，调度高速缓冲存储器的读取机器以获取存储请求的目标存储器块的一致性所有权。 在获取目标存储器块的一致性所有权并且屏障请求已经从存储队列中退出之后，用存储数据更新高速缓冲存储器的高速缓存阵列。

公开(公告)号：US08139592B2

公开(公告)日：2012-03-20

申请号：US12124524

申请日：2008-05-21

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Benjiman L. Goodman ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Benjiman L. Goodman ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： H04L12/28 ,  H04L12/56 ,  G06F13/00 ,  G06F13/28 ,  H04H20/71

CPC分类号： G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.

摘要翻译： 数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送 处理单位。 该通信包括具有请求的操作和表示对请求的系统响应的组合响应。 至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列 在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。 票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

公开(公告)号：US08117397B2

公开(公告)日：2012-02-14

申请号：US12335809

申请日：2008-12-16

申请人： Guy L. Guthrie ,  Thomas L. Jeremiah ,  William L. McNeil ,  Piyush C. Patel ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Guy L. Guthrie ,  Thomas L. Jeremiah ,  William L. McNeil ,  Piyush C. Patel ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0897 ,  Y02D10/13

摘要： A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.

摘要翻译： 高速缓存存储器包括包含多个等同类的高速缓存阵列，每个级别包含多条高速缓存行，其中每条高速缓存行属于至少包括第一类和第二类的多个类中的一个。 缓存存储器还包括指示类成员资格的高速缓存阵列的高速缓存目录。 高速缓冲存储器还包括高速缓存控制器，其选择用于从同余类驱逐的受害缓存行。 如果同余类包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序优先选择属于第二类的同余类的高速缓存行作为受害缓存行。 如果同余类不包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序选择属于第一类的高速缓存行作为受害缓存行。

公开(公告)号：US08099570B2

公开(公告)日：2012-01-17

申请号：US12035695

申请日：2008-02-22

申请人： James A. O'Connor ,  Kanwal Bahri ,  Daniel J. Henderson ,  Luis A. Lastras-Montano ,  Warren E. Maule ,  Michael Mueller ,  Naresh Nayar ,  Richard Nicholas ,  Eric E. Retter ,  William J. Starke ,  Michael R. Trombley ,  Kenneth L. Wright

发明人： James A. O'Connor ,  Kanwal Bahri ,  Daniel J. Henderson ,  Luis A. Lastras-Montano ,  Warren E. Maule ,  Michael Mueller ,  Naresh Nayar ,  Richard Nicholas ,  Eric E. Retter ,  William J. Starke ,  Michael R. Trombley ,  Kenneth L. Wright

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F11/1666 ,  G06F11/1076 ,  G06F11/20 ,  G06F12/0246 ,  G06F2211/1088

摘要： Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.

摘要翻译： 为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。 保留一定量的内存。 用于在保留的存储器中选择镜像的存储器的部分是动态确定的。 存储器的选定部分包含关键区域。 存储器的选定部分被镜像在保留的存储器中。

公开(公告)号：US20110161590A1

公开(公告)日：2011-06-30

申请号：US12650961

申请日：2009-12-31

申请人： Guy L. Guthríe ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthríe ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834

摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.

摘要翻译： 处理单元包括具有确定存在或不存在预留的预约逻辑的存储下位缓存和包括存储通过上级缓存，指令执行单元，负载单元的处理器核心，该负载单元响应于 由指令执行单元通过执行装载预约指令而产生的加载备用操作的上级缓存暂时缓冲加载备用操作的加载目标地址，以及指示载入预约操作被绑定到 上级缓存中的值。 如果接收到与加载保留操作的加载目标地址冲突的存储修改操作，则处理器核心将该标志设置为特定状态，并且响应于执行存储条件指令，发送关联的存储 - 如果该标志被设置为特定状态，则向低级缓存进行条件操作，并显示故障指示。

公开(公告)号：US07944932B2

公开(公告)日：2011-05-17

申请号：US12060751

申请日：2008-04-01

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke

IPC分类号： H04L12/28 ,  G06F15/173 ,  G06F15/76 ,  G06F15/00

CPC分类号： G06F15/16

摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.

摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个处理单元接收的操作广播到多个处理单元中的一个或多个 处理单位。

公开(公告)号：US07747826B2

公开(公告)日：2010-06-29

申请号：US12103564

申请日：2008-04-15

申请人： Jason F. Cantin ,  James S. Fields, Jr. ,  Steven R. Kunkel ,  William J. Starke

发明人： Jason F. Cantin ,  James S. Fields, Jr. ,  Steven R. Kunkel ,  William J. Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。 数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。 相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。