公开(公告)号：US11438414B2

公开(公告)日：2022-09-06

申请号：US16424411

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F15/16 ,  H04L67/1097 ,  G06F12/1027 ,  G06F12/1009 ,  H04L67/51 ,  G06F12/02

Abstract: Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.

公开(公告)号：US11436071B2

公开(公告)日：2022-09-06

申请号：US16553731

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G11C5/06 ,  G06F11/07 ,  G06F11/10 ,  G11C15/04 ,  G11C11/409

Abstract: Methods, systems, and devices for error correction for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.

公开(公告)号：US11422748B2

公开(公告)日：2022-08-23

申请号：US17175911

申请日：2021-02-15

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G11C15/04 ,  G11C13/00

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.

公开(公告)号：US11334387B2

公开(公告)日：2022-05-17

申请号：US16424413

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Dmitri Yudanov

IPC: G06F9/50 ,  G06F12/1009 ,  G06F12/02 ,  H04L41/0896 ,  G06F13/16 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/1036 ,  G06F12/126

Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.

公开(公告)号：US11256624B2

公开(公告)日：2022-02-22

申请号：US16424421

申请日：2019-05-28

Applicant: Micron Technology, inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/0837 ,  G06F12/1027 ,  G06F11/14 ,  G06F9/38 ,  G06F12/1009 ,  G06F13/00 ,  G06F13/28 ,  G06N3/02

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

公开(公告)号：US20220027285A1

公开(公告)日：2022-01-27

申请号：US17496661

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F12/1009 ,  G06F12/1027 ,  G06N5/04 ,  H04L29/08 ,  H04W8/26

Abstract: Systems, methods and apparatuses of fine grain data migration in using Memory as a Service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.

公开(公告)号：US11163490B2

公开(公告)日：2021-11-02

申请号：US16573785

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivam Swami ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  H01L27/24 ,  G06F12/02

Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.

公开(公告)号：US20210089663A1

公开(公告)日：2021-03-25

申请号：US16582871

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Hongyu Wang

IPC: G06F21/60 ,  G06F21/79 ,  H03K19/21

Abstract: Methods and apparatus of Exclusive OR (XOR) engine in a random access memory device to accelerate cryptographical operations in processors. For example, an integrated circuit memory device enclosed within a single integrated circuit package can include an XOR engine that is coupled with memory units in the random access memory device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., System-on-Chip (SoC) or Central Processing Unit (CPU)) can have encryption logic that performs cryptographical operations using XOR operations that are performed by the XOR engine in the random access memory device using the data in the random access memory device.

公开(公告)号：US20210081318A1

公开(公告)日：2021-03-18

申请号：US16573791

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Shivam Swami ,  Sean S. Eilert ,  Samuel E. Bradshaw

IPC: G06F12/06 ,  G06F12/08 ,  G06F12/10 ,  G11C11/00

Abstract: A system having a string of memory chips that can implement flexible provisioning of a multi-tier memory. In some examples, the system can include a first memory chip in a string of memory chips of a memory, a second memory chip in the string, and a third memory chip in the string. The first memory chip can be directly wired to the second memory chip and can be configured to interact directly with the second memory chip. The second memory chip can be directly wired to the third memory chip and can be configured to interact directly with the third memory chip. As part of implementing the flexible provisioning of a multi-tier memory, the first memory chip can include a cache for the second memory chip, and the second memory chip can include a buffer for the third memory chip.

公开(公告)号：US20210073623A1

公开(公告)日：2021-03-11

申请号：US17007588

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C11/4063

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.