公开(公告)号：US11768798B2

公开(公告)日：2023-09-26

申请号：US17550593

申请日：2021-12-14

Applicant: Micron Technology, inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F15/80 ,  G06F16/903 ,  H03K19/17728 ,  G06V10/94 ,  G06V10/70 ,  G06N5/01

CPC classification number: G06F15/80 ,  G06F16/90344 ,  G06N5/01 ,  G06V10/768 ,  G06V10/955 ,  H03K19/17728

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

公开(公告)号：US11599770B2

公开(公告)日：2023-03-07

申请号：US16715755

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F9/448 ,  G06F15/78 ,  G06N3/04 ,  G05B19/045 ,  G06N3/02

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

公开(公告)号：US20230048032A1

公开(公告)日：2023-02-16

申请号：US17979472

申请日：2022-11-02

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit Singh Bains

IPC: G06F12/0875 ,  G06N3/02 ,  G06F3/06 ,  G06F9/448

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

公开(公告)号：US20220261257A1

公开(公告)日：2022-08-18

申请号：US17736399

申请日：2022-05-04

Applicant: Micron Technology Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Giendenning

IPC: G06F9/448 ,  G06F13/42 ,  G06F13/12 ,  G06F13/38 ,  G06F13/28 ,  G06F13/16

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

公开(公告)号：US11410715B2

公开(公告)日：2022-08-09

申请号：US17091969

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  David R. Brown

IPC: G11C11/405 ,  G11C11/406 ,  G06F3/06 ,  H01L25/065

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

公开(公告)号：US11366675B2

公开(公告)日：2022-06-21

申请号：US16525187

申请日：2019-07-29

Applicant: Micron Technology, inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/28 ,  G06F9/448 ,  G06F13/42 ,  G06F13/16

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

公开(公告)号：US11302376B2

公开(公告)日：2022-04-12

申请号：US17002316

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Joo-Sang Lee ,  David R. Brown

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/44 ,  G11C11/4076

Abstract: A memory device includes a memory bank having a set of word lines, a bank control block coupled to the memory bank, wherein the bank control block when in operation provides timing control and data control to facilitate execution of commands to and from the memory bank and a command decoder coupled to the bank control block. The command decoder when in operation transmits to the bank control block a refresh (REF) command associated with a first pump to refresh a memory cell of the memory bank and a row hammer refresh (RHR) command associated with a second pump to refresh a second memory cell of the memory bank in conjunction with a refresh operation, and the bank control block when in operation transmits a first control signal to the command decoder to determine which automatic error check and scrub (AECS) mode operation is selected.

公开(公告)号：US20190354380A1

公开(公告)日：2019-11-21

申请号：US16525187

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F9/448 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38 ,  G06F13/28 ,  G06F13/12

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

公开(公告)号：US20190340130A1

公开(公告)日：2019-11-07

申请号：US16513418

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit Singh Bains

IPC: G06F12/0875 ,  G06F3/06 ,  G06N3/02 ,  G06F9/448

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

公开(公告)号：US10402265B2

公开(公告)日：2019-09-03

申请号：US16030479

申请日：2018-07-09

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.