公开(公告)号：US09196628B1

公开(公告)日：2015-11-24

申请号：US14273206

申请日：2014-05-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/48 ,  H01L27/115 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stepped substack interlayer connector structure on a multilayer integrated circuit includes N steps on the substrate from a surface of the substrate at a first level to a surface of the substrate at a second level. A stack of active layers alternating with insulating layers on the substrate, including a plurality of substacks disposed in relation to the N step(s) to form respective contact regions in which the substacks are disposed at a common level. Interlayer connectors are formed by conductors in the respective regions connected to landing areas on active layers in each of the plurality of substacks. The maximum depth of the interlayer connectors is equal to, or less than, the thickness of one of the substacks.

Abstract translation: 在多层集成电路上的阶梯形层状层间连接器结构包括从第一层的基板的表面到第二层的基板表面的基板上的N个台阶。 一叠有源层与衬底上的绝缘层交替，包括相对于N个步骤设置的多个子区，以形成相应的接触区域，其中子区被布置在共同的水平面上。 中间层连接器由连接到多个子组件中的每一个中的有源层上的着陆区域的相应区域中的导体形成。 层间连接器的最大深度等于或小于其中一个子堆的厚度。

公开(公告)号：US09142538B1

公开(公告)日：2015-09-22

申请号：US14489531

申请日：2014-09-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/02 ,  H01L27/115

CPC classification number: H01L27/0207 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A 3D semiconductor device is provided, comprising memory layers, a selection line, bit lines, strings, memory cells defined by the strings, the selection line, and the bit lines, wherein the memory cells are arranged in a plurality of rows having a first direction, and a stair contact structure including stair contacts and conductive lines, wherein the stair contacts are arranged in a plurality of columns having a fourth direction. The 3D semiconductor device satisfies the following condition: 1

Abstract translation: 提供了一种3D半导体器件，包括存储器层，选择线，位线，串，由串，选择线和位线定义的存储器单元，其中存储器单元被布置成多行，其具有第一 方向以及包括楼梯接触和导线的楼梯接触结构，其中楼梯接触件布置在具有第四方向的多个列中。 3D半导体器件满足以下条件：1

公开(公告)号：US20150206896A1

公开(公告)日：2015-07-23

申请号：US14157550

申请日：2014-01-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.

Abstract translation: 提供了一种3D半导体器件，包括垂直堆叠在衬底上并且彼此平行的多个存储层; 多个选择线设置在存储层上并且彼此平行; 设置在选择线上的多个位线以及与选择线垂直的并行布置的位线; 垂直于存储层和选择线形成的多个串，以及电连接到相应选择线的串; 分别由串，选择线和位线相应地限定的多个单元以及布置成多个行和列的单元，其中列方向平行于位线，而行方向平行于选择 线条。 同一列中的相邻单元电连接到不同的位线。

公开(公告)号：US20150048506A1

公开(公告)日：2015-02-19

申请号：US13965269

申请日：2013-08-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Yen-Hao Shih ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/06 ,  H01L27/105 ,  H01L27/12

CPC classification number: H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，3D存储器阵列，外围电路和导电连接结构。 3D存储器阵列和外围电路堆叠在基板上。 外围电路包括图案化金属层和电连接到图案化金属层的接触结构。 导电连接结构电连接到图案化的金属层。 3D存储器阵列经由导电连接结构电连接到外围电路。

公开(公告)号：US08928149B2

公开(公告)日：2015-01-06

申请号：US13867905

申请日：2013-04-22

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A 3-D structure includes a stack of active layers at different depths has a plurality of contact landing areas on respective active layers within a contact area opening. A plurality of interlayer conductors, each includes a first portion within a contact area opening extending to a contact landing area, and a second portion in part outside the contact area opening above the top active layer. The first portion has a transverse dimension Y1 that is nominally equal to the transverse dimension of the contact area opening, and the second portion having a transverse dimension Y2 that is greater than the transverse dimension of the contact area opening. The active layers can be bit lines or word lines for a 3-D memory device, or other active layers in integrated circuits.

Abstract translation: 3-D结构包括不同深度的有源层堆叠在接触区域开口内的相应有源层上具有多个接触着陆区域。 多个层间导体各自包括在延伸到接触着陆区域的接触区域开口内的第一部分和位于顶部活性层上方的接触区域的部分外部的第二部分。 第一部分具有名义上等于接触区域开口的横向尺寸的横向尺寸Y1，并且第二部分具有大于接触区域开口的横向尺寸的横向尺寸Y2。 有源层可以是用于3-D存储器件或集成电路中的其它有源层的位线或字线。

公开(公告)号：US08916924B2

公开(公告)日：2014-12-23

申请号：US14165611

申请日：2014-01-28

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7926 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7827

Abstract: A method for manufacturing semiconductor device is disclosed. A substrate with a plurality of protruding strips formed vertically thereon is provided. A charging trapping layer is formed conformally on the protruding strips. A conductive layer is formed conformally on the charging trapping layer. A thin hard mask is conformally deposited on the conductive layer, wherein a plurality of trenches are formed between the thin hard mask on the protruding strips. A patterned photo resist is formed on the thin hard mask, wherein the patterned photo resist fills into the trenches. The thin hard mask is patterned according to the patterned photo resist to form a patterned hard mask layer and expose a portion of the conductive layer. The conductive layer is patterned for removing the exposed portion of the conductive layer to form a patterned conductive layer and expose a portion of the charging trapping layer.

Abstract translation: 公开了半导体器件的制造方法。 提供了具有垂直形成的多个突出条的基板。 充电捕获层在突出条上保形地形成。 在充电捕集层上保形地形成导电层。 在导电层上共形沉积薄的硬掩模，其中在突出条上的薄硬掩模之间形成多个沟槽。 在薄的硬掩模上形成图案化的光致抗蚀剂，其中图案化的光致抗蚀剂填充到沟槽中。 根据图案化的光致抗蚀剂对薄的硬掩模进行图案化，以形成图案化的硬掩模层并暴露导电层的一部分。 图案化导电层以去除导电层的暴露部分以形成图案化的导电层并暴露一部分充电捕获层。

公开(公告)号：US08815655B2

公开(公告)日：2014-08-26

申请号：US13727139

申请日：2012-12-26

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L21/84

CPC classification number: H01L29/7926 ,  H01L21/32139 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

Abstract: A method for manufacturing semiconductor device is disclosed. A substrate with a conductive layer is provided, and a dummy layer is formed on the conductive layer. The dummy layer and at least a portion of the conductive layer are patterned to form several trenches. A first dielectric layer is formed to fill into the trenches so as to form several first dielectric elements in the trenches. The dummy layer is removed to expose parts of the first dielectric elements. A second dielectric layer is formed on the exposed parts of the first dielectric elements, and the second dielectric layer is patterned so that a spacer is formed at a lateral side of each exposed first dielectric element. The conductive layer is patterned by the spacers, so that a patterned conductive portion is formed at each lateral side of each first dielectric element.

Abstract translation: 公开了半导体器件的制造方法。 提供具有导电层的基板，并且在导电层上形成虚设层。 虚拟层和导电层的至少一部分被图案化以形成几个沟槽。 形成第一电介质层以填充到沟槽中，以在沟槽中形成几个第一介电元件。 去除虚设层以露出第一电介质元件的部分。 在第一电介质元件的暴露部分上形成第二电介质层，并且图案化第二电介质层，使得在每个暴露的第一介电元件的侧面形成间隔物。 导电层通过间隔物图案化，使得在每个第一介电元件的每个横向侧上形成图案化的导电部分。

公开(公告)号：US20140191388A1

公开(公告)日：2014-07-10

申请号：US13736104

申请日：2013-01-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L21/76838 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A 3D stacking semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. N layers of stacking structures are provided. Each stacking structure includes a conductive layer and an insulating layer. A first photoresister layer is provided. The stacking structures are etched P−1 times by using the first photoresister layer as a mask. A second photoresister layer is provided. The stacking structures are etched Q−1 times by using the second photoresister layer as a mask. The first photoresister layer is trimmed along a first direction. The second photoresister layer is trimmed along a second direction. The first direction is different from the second direction. A plurality of contact points are arranged along the first and the second directions in a matrix. The included angle between the first direction and the second direction is an acute angle.

Abstract translation: 提供了3D堆叠半导体器件及其制造方法。 该制造方法包括以下步骤。 提供N层堆叠结构。 每个堆叠结构包括导电层和绝缘层。 提供第一光致抗蚀剂层。 通过使用第一光致抗蚀剂层作为掩模，将堆叠结构蚀刻P-1次。 提供第二光致抗蚀剂层。 通过使用第二光致抗蚀剂层作为掩模，将堆叠结构蚀刻Q-1次。 沿着第一方向修剪第一光致抗蚀剂层。 沿着第二方向修剪第二光致抗蚀剂层。 第一个方向与第二个方向不同。 沿着第一和第二方向以矩阵形式布置多个接触点。 第一方向和第二方向之间的夹角是锐角。

公开(公告)号：US20140053979A1

公开(公告)日：2014-02-27

申请号：US14070333

申请日：2013-11-01

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L21/67

CPC classification number: H01L21/67069 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x-1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.

Abstract translation: 三维堆叠IC器件在互连区域具有一层接触电平。 根据本发明的一些示例，其仅需要一组N个蚀刻掩模以在接触电平的堆叠处产生多达且包括2N级的互连接触区域。 根据一些示例，对于每个掩码序列号x蚀刻2x-1接触电平，x是掩模的序列号，使得对于一个掩模x = 1，对于另一个掩模x = 2，依此类推，x = N 。 方法创建互连接触区域与接触层面上的着陆区域对齐。

公开(公告)号：US08604555B1

公开(公告)日：2013-12-10

申请号：US13649232

申请日：2012-10-11

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen ,  Kuang-Yeu Hsieh

IPC: H01L29/94

CPC classification number: H01L29/42384 ,  H01L29/41733 ,  H01L29/78654

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a gate dielectric layer, a gate structure, a source conductive structure, a drain conductive structure, and a gate conductive structure. The substrate has a channel area. The gate dielectric layer is formed on the channel area, and the gate structure is formed on the gate dielectric layer. The source conductive structure and the drain conductive structure penetrate through the gate structure and are electrically connected to the substrate, and the source conductive structure and the drain conductive structure are electrically isolated from the gate structure. The gate conductive structure is formed on the gate structure. The source conductive structure and the drain conductive structure are separated by a distance which is equal to a length of the channel area.

Abstract translation: 提供了一种半导体结构及其制造方法。 该半导体结构包括衬底，栅极电介质层，栅极结构，源极导电结构，漏极导电结构和栅极导电结构。 衬底具有通道面积。 栅介质层形成在沟道区上，栅极结构形成在栅介质层上。 源极导电结构和漏极导电结构穿过栅极结构并且电连接到衬底，并且源极导电结构和漏极导电结构与栅极结构电隔离。 栅极导电结构形成在栅极结构上。 源极导电结构和漏极导电结构被分开等于沟道面积的长度的距离。