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    Classification model training using diverse training source and inference engine using same
    1.
    发明授权
    Classification model training using diverse training source and inference engine using same 有权

    公开(公告)号：US11775822B2

    公开(公告)日：2023-10-03

    申请号：US16885638

    申请日：2020-05-28

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Shih-Hung Chen ,  Tzu-Hsiang Su

    IPC分类号： G06N3/08 ,  G06N3/04

    CPC分类号： G06N3/08 ,  G06N3/04

    摘要： A method for generating a classification model using a training data set. An iterative procedure for training an ANN model, in which an iteration includes selecting a small sample of training data from a source of training data, training the model using the sample, using the model in inference mode over a larger sample of the training data, and reviewing the results of the inferencing. The results can be evaluated to determine whether the model is satisfactory, and if it does not meet specified criteria, then cycles of sampling, training, inferencing and reviewing results (STIR cycles) are repeated in an iterative process until the criteria are met. A classification engine trained as described herein is provided.

    Memory device
    2.
    发明授权
    Memory device 有权

    公开(公告)号：US11289130B2

    公开(公告)日：2022-03-29

    申请号：US16997986

    申请日：2020-08-20

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Shih-Hung Chen

    IPC分类号： H01L23/538 ,  G11C5/06 ,  G11C5/02 ,  H01L25/065

    摘要： A memory device includes a periphery wafer, a memory array chip stack, and a plurality of first conductive contacts. The periphery wafer has a functional surface. The memory array chip stack is disposed on the periphery wafer and has a functional surface, in which the functional surface of the periphery wafer faces toward the functional surface of the memory array chip stack, and a first side of the memory array chip stack is in a staircase configuration. The first conductive contacts are on the first side of the memory array chip stack, and between and interconnecting the functional surface of the periphery wafer and the functional surface of the memory array chip stack.

    CONNECTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME
    5.
    发明申请
    CONNECTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
    连接器结构及其制造方法

    公开(公告)号：US20170047245A1

    公开(公告)日：2017-02-16

    申请号：US14826257

    申请日：2015-08-14

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Shih-Hung Chen

    IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

    CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L27/11582 ,  H01L28/00

    摘要： A connector structure for electrically contacting with a conductive layer disposed on a substrate is provided. The connector structure comprises a conductive connecting element disposed on the substrate. The conductive connecting element comprises a connecting part and an extending part. The connecting part has a bottom portion electrically contacting with the conductive layer. The extending part laterally extends outwards from a top portion of the connecting part, and the extending part and the connecting part are respectively formed of different materials.

    摘要翻译： 提供了一种用于与设置在基板上的导电层电接触的连接器结构。 连接器结构包括设置在基板上的导电连接元件。 导电连接元件包括连接部分和延伸部分。 连接部分具有与导电层电接触的底部部分。 延伸部分从连接部分的顶部向外侧向延伸，并且延伸部分和连接部分分别由不同的材料形成。

    Memory structure
    7.
    发明授权
    Memory structure 有权
    内存结构

    公开(公告)号：US09542979B1

    公开(公告)日：2017-01-10

    申请号：US14834475

    申请日：2015-08-25

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Shih-Hung Chen

    IPC分类号： G11C5/02 ,  G11C8/10 ,  G11C8/08

    CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

    摘要： A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer ≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=⅕ to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines.

    摘要翻译： 存储器结构包括分别与N个阵列区域耦合的N个阵列区域和N个页面缓冲器。 N为整数≥2。 N个阵列区域中的每一个包括多个存储单元的3D阵列。 存储单元在3D阵列的水平单元平面上具有两个相邻存储单元之间的横向距离d。 N个阵列区域中的每一个还包括多条导线。 导线布置在3D阵列上并耦合到3D阵列。 导线具有间距p，p / d =⅕至½。 N个阵列区域和N个页面缓冲器沿着导电线的延伸方向布置在一条线上。

    Semiconductor apparatus and manufacturing method of the same
    10.
    发明授权
    Semiconductor apparatus and manufacturing method of the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09293471B1

    公开(公告)日：2016-03-22

    申请号：US14524066

    申请日：2014-10-27

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Shih-Hung Chen

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L29/49 ,  H01L21/768 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/76816 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4975 ,  H01L29/7926

    摘要： A semiconductor apparatus including a first stacked structure and a second stacked structure is provided. The first stacked structure and the second stacked structure are arranged along a first direction, and extended along a second direction perpendicular to the first direction. The first stacked structure includes a first operating portion and a first supporting portion. The first operating portion and the first supporting portion are alternately arranged along the second direction. A width of the first operating portion along the first direction is smaller than a width of the first supporting portion along the first direction.

    摘要翻译： 提供了包括第一堆叠结构和第二堆叠结构的半导体装置。 第一堆叠结构和第二堆叠结构沿着第一方向布置，并且沿着垂直于第一方向的第二方向延伸。 第一堆叠结构包括第一操作部分和第一支撑部分。 第一操作部分和第一支撑部分沿着第二方向交替布置。 沿着第一方向的第一操作部的宽度小于第一支撑部沿着第一方向的宽度。