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    Display system with first controller providing analog image signal from size regulator to display device when the first controller determining that the display device is an analog display device working in a mode for displaying moving pictures and related display method
    101.
    发明授权
    Display system with first controller providing analog image signal from size regulator to display device when the first controller determining that the display device is an analog display device working in a mode for displaying moving pictures and related display method 有权
    具有第一控制器的显示系统，当第一控制器确定显示设备是以用于显示运动图像的模式工作的模拟显示设备和相关显示方法时，从尺寸调节器向显示设备提供模拟图像信号

    公开(公告)号：US08274498B2

    公开(公告)日：2012-09-25

    申请号：US11982870

    申请日：2007-11-05

    Applicant: Gang-Qiang Zheng ,  Bin Yang

    Inventor： Gang-Qiang Zheng ,  Bin Yang

    IPC: G09G5/00

    CPC classification number: H04N5/2628 ,  H04N2101/00

    Abstract: An exemplary display system (2) includes a display device (23), an image sensor (20), and a microprocessor unit (21). The image sensor includes an image sensor unit (24) and a digital signal processor unit (22) integrated therein. The image sensor unit is configured for generating a current. The digital signal processor includes a size regulator (221) configured for receiving the current, generating an analog image signal according to the current, and providing the analog image signal to the display device. The microprocessor unit is configured for initializing the image sensor unit.

    Abstract translation: 示例性显示系统（2）包括显示设备（23），图像传感器（20）和微处理器单元（21）。 图像传感器包括集成在其中的图像传感器单元（24）和数字信号处理器单元（22）。 图像传感器单元被配置为产生电流。 数字信号处理器包括：尺寸调节器（221），被配置为接收电流，根据电流产生模拟图像信号，并将模拟图像信号提供给显示装置。 微处理器单元被配置为初始化图像传感器单元。

    Metal-Semiconductor Intermixed Regions
    102.
    发明申请
    Metal-Semiconductor Intermixed Regions 有权

    公开(公告)号：US20120190192A1

    公开(公告)日：2012-07-26

    申请号：US13012043

    申请日：2011-01-24

    Applicant: Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    Inventor： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    IPC: H01L21/44

    CPC classification number: H01L21/28518

    Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

    METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE
    103.
    发明申请
    METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE 有权
    控制金属半导体微结构的方法

    公开(公告)号：US20120181697A1

    公开(公告)日：2012-07-19

    申请号：US13006664

    申请日：2011-01-14

    Applicant: Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

    Inventor： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

    IPC: H01L23/532 ,  H01L21/768

    CPC classification number: H01L21/768 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

    Abstract translation: 一种形成金属半导体合金的方法，其包括在半导体衬底的第一深度上形成混合金属半导体区域而没有热扩散。 将混合后的金属半导体区域退火以形成织构化的金属半导体合金。 在纹理金属半导体合金上形成第二金属层。 纹理金属半导体合金上的第二金属层然后退火以形成金属半导体合金接触，其中来自第二金属层的金属元素通过织构化金属半导体合金扩散以提供模板化的金属半导体合金。 模板化金属半导体合金的厚度范围为15nm〜50nm的金属半导体合金的晶粒尺寸大于2×。

    SOI Schottky Source/Drain Device Structure to Control Encroachment and Delamination of Silicide
    106.
    发明申请
    SOI Schottky Source/Drain Device Structure to Control Encroachment and Delamination of Silicide 失效
    SOI肖特基源/排水装置结构，以控制硅化物的侵蚀和分层

    公开(公告)号：US20110227156A1

    公开(公告)日：2011-09-22

    申请号：US12726789

    申请日：2010-03-18

    Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

    Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

    IPC: H01L27/12

    CPC classification number: H01L29/78654 ,  H01L29/7839

    Abstract: A Schottky field effect transistor is provided that includes a substrate having a layer of semiconductor material atop a dielectric layer, wherein the layer of semiconductor material has a thickness of less than 10.0 nm. A gate structure is present on the layer of semiconductor material. Raised source and drain regions comprised of a metal semiconductor alloy are present on the layer of semiconductor material on opposing sides of the gate structure. The raised source and drain regions are Schottky source and drain regions. In one embodiment, a first portion of the Schottky source and drain regions that is adjacent to a channel region of the Schottky field effect transistor contacts the dielectric layer, and a non-reacted semiconductor material is present between a second portion of the Schottky source and drain regions and the dielectric layer.

    Abstract translation: 提供一种肖特基场效应晶体管，其包括在电介质层顶上具有半导体材料层的衬底，其中半导体材料层的厚度小于10.0nm。 栅极结构存在于半导体材料层上。 在栅极结构的相对侧的半导体材料层上存在由金属半导体合金构成的凸起的源极和漏极区域。 凸起的源极和漏极区域是肖特基源极和漏极区域。 在一个实施例中，与肖特基场效应晶体管的沟道区相邻的肖特基源极和漏极区的第一部分接触电介质层，并且未反应的半导体材料存在于肖特基源的第二部分和 漏区和电介质层。

    NMOS ARCHITECTURE INVOLVING EPITAXIALLY-GROWN IN-SITU N-TYPE-DOPED EMBEDDED eSiGe:C SOURCE/DRAIN TARGETING
    108.
    发明申请
    NMOS ARCHITECTURE INVOLVING EPITAXIALLY-GROWN IN-SITU N-TYPE-DOPED EMBEDDED eSiGe:C SOURCE/DRAIN TARGETING 有权
    涉及外延生长的N型掺杂嵌入式的NMOS结构eSiGe：C源/漏极区

    公开(公告)号：US20110133189A1

    公开(公告)日：2011-06-09

    申请号：US12632351

    申请日：2009-12-07

    Applicant: Bin Yang ,  Bo Bai

    Inventor： Bin Yang ,  Bo Bai

    IPC: H01L29/772 ,  H01L21/20

    CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

    Abstract: An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduction in extension silicon and dopant loss, improved morphology, increased wafer throughput, improved short channel control, and reduced silicide to source/drain contact resistance.

    Abstract translation: 形成具有改进的可制造性的NMOS晶体管。 实施例包括在衬底的源极/漏极区域中形成含有N型掺杂的含硅锗（eSiGe：C），并使eSiGe：C非晶化。 eSiGe：C的使用提供了延长硅和掺杂剂损耗的减少，改进的形态，增加的晶片产量，改进的短沟道控制以及降低的硅化物到源/漏接触电阻。

    Lignin blockers and uses thereof
    109.
    发明授权
    Lignin blockers and uses thereof 有权
    木质素阻滞剂及其用途

    公开(公告)号：US07875444B2

    公开(公告)日：2011-01-25

    申请号：US11229817

    申请日：2005-09-19

    Applicant: Bin Yang ,  Charles E. Wyman

    Inventor： Bin Yang ,  Charles E. Wyman

    IPC: C12P7/06 ,  C12P7/08 ,  C12P7/10 ,  C12P19/14 ,  C12P21/06 ,  C07K14/415 ,  C07K14/765

    CPC classification number: C12P7/10 ,  C12P7/08 ,  C12P19/02 ,  Y02E50/16 ,  Y02E50/17

    Abstract: Disclosed is a method for converting cellulose in a lignocellulosic biomass. The method provides for a lignin-blocking polypeptide and/or protein treatment of high lignin solids. The treatment enhances cellulase availability in cellulose conversion and allows for the determination of optimized pretreatment conditions. Additionally, ethanol yields from a Simultaneous Saccharification and Fermentation process are improved 5-25% by treatment with a lignin-blocking polypeptide and/or protein. Thus, a more efficient and economical method of processing lignin containing biomass materials utilizes a polypeptide/protein treatment step that effectively blocks lignin binding of cellulase.

    Abstract translation: 公开了一种在木质纤维素生物质中转化纤维素的方法。 该方法提供高木质素固体的木质素阻断多肽和/或蛋白质处理。 该处理增强了纤维素转化中的纤维素酶可用性，并且允许确定优化的预处理条件。 此外，通过用木质素阻断多肽和/或蛋白质处理，来自同时糖化和发酵过程的乙醇产率提高了5-25％。 因此，处理含木质素的生物质材料的更有效和经济的方法利用有效阻断木质素结合纤维素酶的多肽/蛋白质处理步骤。

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