公开(公告)号：US20220269509A1

公开(公告)日：2022-08-25

申请号：US17743062

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US11380372B1

公开(公告)日：2022-07-05

申请号：US17124697

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Timothy P. Finkbeiner ,  Troy A. Manning ,  Troy D. Larsen ,  Glen E. Hush

IPC: G11C7/06 ,  G11C7/10

Abstract: Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).

公开(公告)号：US11354187B2

公开(公告)日：2022-06-07

申请号：US16871641

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G06F8/41

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

公开(公告)号：US20210365383A1

公开(公告)日：2021-11-25

申请号：US17324250

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Harold Robert G. Trout ,  Timothy P. Finkbeiner ,  Troy A. Manning ,  Glen E. Hush ,  Troy D. Larsen

IPC: G06F12/10 ,  G11C15/04

Abstract: Apparatuses, systems, and methods for mapping a virtual address using a CAM are described. A parallel structure of a CAM can enable functions of a MMU to be integrated into a single operation performed using the CAM such that a virtual address of a memory array can be mapped directly to a row of a memory. An example method includes receiving an access command and address information for a memory array; identifying a virtual address and a physical address of the memory array based on the received address information; comparing, during a time period associated with the access command, the virtual address and the physical address to virtual addresses and physical addresses, respectively, of the memory array stored in a CAM; and accessing, during the time period, a row of the memory array coupled to a row of the CAM storing the virtual address and the physical address.

公开(公告)号：US20210365363A1

公开(公告)日：2021-11-25

申请号：US17324327

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Harold Robert G. Trout ,  Glen E. Hush ,  Troy A. Manning ,  Troy D. Larsen ,  Timothy P. Finkbeiner

IPC: G06F12/02 ,  G06F12/06 ,  G11C15/04 ,  G11C5/06 ,  H03K19/21

Abstract: Methods, apparatuses, and systems related to mapping a virtual address using a physical address are described. In a memory system including a memory (e.g., cache) and a content addressable memory (CAM), the CAM can be configured to search data requested by a host from the memory based on multiple indicators stored in the CAM. For example, in the event that the data stored in the memory is not searchable based on a particular indicator such as a virtual address of a memory array (e.g., main memory), the CAM be configured to search the data based on another indicator such as a physical address of the memory array. Searching the data based on multiple indicators can resolve a synonym problem.

公开(公告)号：US20210118478A1

公开(公告)日：2021-04-22

申请号：US17135802

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/22 ,  G06F12/00 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G06F3/06 ,  G06F7/523 ,  H03K19/1776 ,  H03K19/00 ,  G11C7/10

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

公开(公告)号：US10782980B2

公开(公告)日：2020-09-22

申请号：US16112577

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US10249350B2

公开(公告)日：2019-04-02

申请号：US15642723

申请日：2017-07-06

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Richard C. Murphy

IPC: G11C29/00 ,  G11C7/06 ,  G06F11/10 ,  G11C7/10 ,  G11C7/22 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.

公开(公告)号：US10210911B2

公开(公告)日：2019-02-19

申请号：US15692003

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Troy A. Manning

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/16 ,  G11C7/06

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.

公开(公告)号：US10186303B2

公开(公告)日：2019-01-22

申请号：US15899187

申请日：2018-02-19

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C16/04 ,  H03K19/00 ,  G11C7/22 ,  G06F12/00 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G06F3/06 ,  G06F7/523 ,  G11C7/10 ,  H03K19/177

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.