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公开(公告)号：US20200044613A1
公开(公告)日：2020-02-06
申请号：US16293666
申请日：2019-03-06
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Hung-Chia Lo , Tien-Yun Peng
Abstract: An impedance circuit includes a first impedance terminal, a second impedance terminal, a first transistor, a second transistor, a low frequency signal blocking element, and a current-voltage transform circuit. The first transistor is coupled to the first impedance terminal, and controlled by a first voltage. The second transistor is coupled to the first impedance terminal, and controlled by a second voltage. The low frequency signal blocking element is coupled to the first transistor and the second impedance terminal. The current-voltage transform circuit is coupled to the first impedance terminal. The current-voltage transform circuit adjusts a terminal voltage at the first terminal of the current-voltage transform circuit according to a current flowing through the current-voltage transform circuit. The impedance circuit provides impedance between the first and the second impedance terminals according to the terminal voltage and the first voltage.
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公开(公告)号：US10510748B2
公开(公告)日：2019-12-17
申请号：US15638351
申请日：2017-06-29
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Tsung-Han Lee , Chang-Yi Chen
IPC: H01L27/06
Abstract: A transistor includes a first doping well, a second doping well, a first doping area, a second doping area, a gate layer, and at least one compensation capacitor. The first doping well and the second doping well are formed in a structure layer. The first doping area and the second doping area are formed in the first doping well and have a first conductivity type, the second doping well has a second conductivity type, and the first doping area is used for transmitting the signal. The at least one compensation capacitor is used for adjusting a voltage drop of a parasitic junction capacitor between the first doping area and the first doping well, a voltage drop of a parasitic junction capacitor between the first doping well and the second doping well, or a voltage drop of a parasitic junction capacitor between the second doping well and the structure layer.
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公开(公告)号：US20190267949A1
公开(公告)日：2019-08-29
申请号：US16406026
申请日：2019-05-08
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Hung-Chia Lo , Tien-Yun Peng
Abstract: An amplifier device includes an amplifying unit, a bias module, an impedance unit and an adjusting module. The amplifying unit has a first end coupled to a voltage source and used for outputting an output signal amplified by the amplifying unit, a second end used for receiving an input signal, and a third end coupled to a first reference potential terminal. The bias module is coupled to the second end of the amplifying unit, and provides a bias voltage to the amplifying unit and adjusts linearity of the amplifier device according to a source voltage from the voltage source. The impedance unit is coupled to the bias module and used to receive a control voltage to adjust an impedance value of the impedance unit. The adjusting module is used to output the control voltage to the impedance unit according to the source voltage and a reference voltage.
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公开(公告)号：US10291189B2
公开(公告)日：2019-05-14
申请号：US15730241
申请日：2017-10-11
Applicant: RICHWAVE TECHNOLOGY CORP.
Inventor： Chih-Sheng Chen , Chia-Jung Yeh
Abstract: An amplification circuit includes a first amplifier circuit and a second-stage amplifier. The second-stage amplifier is connected to the amplifier to form a multi-stage amplification circuit. The first amplifier circuit includes a first-stage amplifier and a bypass circuit. The bypass circuit includes a first transistor. A first end of the first transistor is coupled to the input end of the first amplifier circuit, a second end of the first transistor is coupled to the output end of the first amplifier circuit, and a third end of the first transistor is coupled to a supply voltage. The first end of the first transistor is further coupled to a first control terminal to receive a control signal for controlling a bias voltage of the first transistor, so as to make the amplification circuit work in different operation modes.
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公开(公告)号：US10284084B2
公开(公告)日：2019-05-07
申请号：US15844598
申请日：2017-12-17
Applicant: RICHWAVE TECHNOLOGY CORP.
Inventor： Chih-Sheng Chen , Sheng-Tsung Wang
Abstract: A power control circuit provides a supply voltage, and includes a voltage regulating circuit and a signal selecting circuit. The voltage regulating circuit is coupled to a power supply voltage and the output end of the power control circuit, and receives a first control signal for outputting the supply voltage. The signal selecting circuit has a first input end, a second input end and a third input end. The first input end of the signal selecting circuit receives a first input signal, the second input end of the signal selecting circuit receives a second input signal, and the third input end of the signal selecting circuit receives a second control signal. The first input signal is related to the power supply voltage. One of the first input signal and the second input signal is chosen and outputted as the first control signal according to the second control signal.
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Patent Agency Ranking
公开(公告)号：US20180329443A1
公开(公告)日：2018-11-15
申请号：US15810148
申请日：2017-11-13
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Tien-Yun Peng
CPC classification number: G05F3/262 , H03F1/0205 , H03F1/223 , H03F3/193 , H03F3/195 , H03F2200/168 , H03F2200/18 , H03F2200/267 , H03F2200/301 , H03F2200/312 , H03F2200/451
Abstract: A current mirror device includes an input end for receiving an input signal, an output end for outputting an amplified signal of the input signal, first through third transistors, and an operational amplifier. The first transistor includes a first end coupled to first reference current and a second end coupled to a bias voltage. The control end of the second transistor is coupled to the input end. The third transistor includes a first end coupled to the output end, a second end coupled to the first end of the second transistor and a control end coupled to a reference voltage. The operational amplifier is configured to keep a first voltage and a second voltage at substantially the same level, wherein the first voltage is obtained on the first end of the first transistor and the second voltage is obtained on the first end of the second transistor. Therefore, the reference current flowing through the first transistor can be accurately amplified to a desired value and mirrored to become load current flowing through the second transistor.
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107.发明申请公开(公告)号：US20180323780A1
公开(公告)日：2018-11-08
申请号：US15825116
申请日：2017-11-29
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Tien-Yun Peng
Abstract: A bandgap reference circuit includes a voltage generation circuit, a capacitor and a clamping control circuit. The voltage generation circuit is used to generate a current on an operation terminal. The capacitor includes a first terminal coupled to the operation terminal, and a second terminal coupled to a first reference voltage terminal. The clamping control circuit is coupled between the operation terminal and a second reference voltage terminal. The clamping control circuit includes a switch and a clamping unit, and is used to allow part of the current flowing through the clamping unit to the second reference voltage terminal when the switch is turned on.
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公开(公告)号：US20180294778A1
公开(公告)日：2018-10-11
申请号：US16008054
申请日：2018-06-14
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Chang-Yi Chen
CPC classification number: H03F1/56 , H03F1/0277 , H03F1/223 , H03F3/16 , H03F3/193 , H03F3/72 , H03F2200/294 , H03F2200/387 , H03F2200/555 , H03F2203/7239
Abstract: An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.
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公开(公告)号：US20170279417A1
公开(公告)日：2017-09-28
申请号：US15469566
申请日：2017-03-26
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Chang-Yi Chen
CPC classification number: H03F1/56 , H03F1/0277 , H03F1/223 , H03F3/16 , H03F3/193 , H03F3/72 , H03F2200/294 , H03F2200/387 , H03F2200/555 , H03F2203/7239
Abstract: An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.
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公开(公告)号：US20170272059A1
公开(公告)日：2017-09-21
申请号：US15201520
申请日：2016-07-04
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Ching-Wen Hsu , Chien-Yu Li
CPC classification number: H03K3/012 , H03F1/223 , H03F1/565 , H03F3/193 , H03F3/72 , H03F2200/222 , H03F2200/451 , H03F2203/7233 , H03H11/28 , H03K17/16 , H04B1/18
Abstract: An active circuit includes an active element, an input unit, and a bypass unit. The active element is coupled to an output terminal of the active circuit for outputting an output signal. The input unit is coupled to an input terminal of the active circuit, and is coupled to an input terminal of the active element through a node. The input unit adjusts a capacitance value of the input unit according to a first control signal. The bypass unit is coupled to an output terminal of the input unit through the node, and is coupled to the output terminal of the active circuit. The bypass unit turns on or off a signal bypassing path according to a second control signal.
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