公开(公告)号：US20130017665A1

公开(公告)日：2013-01-17

申请号：US13380807

申请日：2011-08-05

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： The present invention relates to a method of forming an isolation structure and a semiconductor structure. The method of forming the isolation structure comprises the steps of: providing a silicon substrate having a (110) crystal plane or a (112) crystal plane and determining the [111] direction of the silicon substrate; forming first trenches in the silicon substrate by wet etching the silicon substrate, the extension direction of the first trenches being substantially perpendicular to the [111] direction; filling the first trenches with a first insulating material to form a first isolator; forming second trenches in the silicon substrate by dry etching the silicon substrate, the extension direction of the second trenches being perpendicular to the extension direction of the first trenches; filling the second trenches with a second insulating material to form a second isolator.

摘要翻译： 本发明涉及形成隔离结构和半导体结构的方法。 形成隔离结构的方法包括以下步骤：提供具有（110）晶面或（112）晶面并确定硅衬底的[111]方向的硅衬底; 通过湿蚀刻硅衬底在硅衬底中形成第一沟槽，第一沟槽的延伸方向基本上垂直于[111]方向; 用第一绝缘材料填充第一沟槽以形成第一隔离器; 通过干蚀刻硅衬底在硅衬底中形成第二沟槽，第二沟槽的延伸方向垂直于第一沟槽的延伸方向; 用第二绝缘材料填充第二沟槽以形成第二隔离器。

公开(公告)号：US08354343B2

公开(公告)日：2013-01-15

申请号：US12990990

申请日：2010-09-19

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L23/48

CPC分类号： H01L23/522 ,  H01L21/32051 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.

摘要翻译： 本发明提供一种半导体结构及其制造方法。 该方法包括：提供包括半导体器件的半导体衬底; 在所述半导体衬底上沉积铜扩散阻挡层; 在铜扩散阻挡层上形成铜复合层; 根据铜互连的形状，将要形成铜互连的相应位置处的铜复合物分解成铜; 并且在下面蚀刻未分解的铜复合物和铜扩散阻挡层，以使半导体器件互连。 本发明适用于制造集成电路中的互连。

公开(公告)号：US20130009217A1

公开(公告)日：2013-01-10

申请号：US13378997

申请日：2011-08-09

申请人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659

摘要： It is provided a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. A method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack, a primary spacer, and source/drain regions, wherein the primary spacer surrounds the gate stack, and the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer; forming a semiconductor spacer surrounding the primary spacer, and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other; and covering the surfaces of the source/drain regions and the semiconductor spacer with a layer of metal or alloy, and annealing the resulting structure, so that a metal silicide is formed on the surfaces of the source/drain regions, and so that the semiconductor spacer is transformed into a silicide spacer simultaneously. As such, the risk of transistor failure due to atoms or ions of Ni entering the channel region through the source/drain extension regions is reduced.

摘要翻译： 提供晶体管，晶体管的制造方法和包括晶体管的半导体芯片。 一种用于制造晶体管的方法可以包括：在半导体衬底上限定有源区，以及在有源区上形成栅极堆叠，初级间隔物和源极/漏极区，其中主要间隔物包围栅极堆叠，源极 /漏极区域嵌入有源区域并与主间隔物的相对侧自对准; 形成围绕所述初级间隔物的半导体衬垫，并且在所述栅极叠层的宽度方向上切断所述半导体衬垫的端部，以将所述源极/漏极区彼此隔离; 并且用金属或合金层覆盖源极/漏极区域和半导体衬垫的表面，并对所得结构进行退火，使得在源极/漏极区域的表面上形成金属硅化物，并且使得半导体 间隔物同时转化成硅化物间隔物。 因此，由于通过源极/漏极延伸区域进入沟道区域的Ni的原子或离子导致的晶体管故障的风险降低。

公开(公告)号：US20120319213A1

公开(公告)日：2012-12-20

申请号：US13380486

申请日：2011-04-18

申请人： Haizhou Yin ,  Wei Jiang ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Wei Jiang ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/41775 ,  H01L29/456 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure. The present invention is beneficial to the suppression of the diffusion of corresponding compositions from the contact layers into the channel region, reduction of the short channel effects, and improvement of the reliability of the semiconductor structure.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括：在第一间隔物的暴露的有源区上形成第一接触层; 在所述第一接触层的靠近栅极堆叠的区域处形成第二间隔物以部分地覆盖所述暴露的有源区; 在未覆盖的暴露的有源区中形成第二接触层，其中当第一接触层的扩散系数与第二接触层的扩散系数相同时，第一接触层的厚度小于第二接触层的厚度; 并且当第一接触层的扩散系数与第二接触层的扩散系数不同时，第一接触层的扩散系数小于第二接触层的扩散系数。 相应地，本发明还提供一种半导体结构。 本发明有利于抑制相应组合物从接触层扩散到沟道区中，减少短沟道效应，提高半导体结构的可靠性。

公开(公告)号：US20120273901A1

公开(公告)日：2012-11-01

申请号：US13063733

申请日：2010-09-27

申请人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/49 ,  H01L29/66583 ,  H01L29/7833

摘要： The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, when a gate is formed via a replacement gate process, a portion of a work function metal layer and a portion of a first metal layer are removed after the work function metal layer and the first metal layer are formed, and then the removed portions are replaced with a second metal layer. A device having such a gate structure greatly reduces the resistivity of the whole gate, due to a portion of the work function metal layer with a high resistivity being removed and the removed portion being filled with the second metal layer with a low resistivity, thereby AC performances of the device are improved.

摘要翻译： 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 根据本发明，当通过替换栅极工艺形成栅极时，在形成功函数金属层和第一金属层之后，去除功函数金属层的一部分和第一金属层的一部分，以及 然后用第二金属层代替去除的部分。 具有这种栅极结构的器件大大降低了整个栅极的电阻率，这是由于去除具有高电阻率的功函数金属层的一部分并且被去除的部分被低电阻率的第二金属层填充，由此AC 改善了设备的性能。

公开(公告)号：US20120261674A1

公开(公告)日：2012-10-18

申请号：US13378253

申请日：2011-03-02

申请人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

发明人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/78

摘要： The present invention provides a semiconductor device, which is formed on a semiconductor substrate, comprising a gate stack, a channel region, and source/drain regions, wherein the gate stack is on the channel region, the channel region is in the semiconductor substrate, the source/drain regions are embedded in the semiconductor substrate, and each of the source/drain regions comprises a sidewall and a bottom, a second semiconductor layer being sandwiched between the channel region and a portion of the sidewall distant from the bottom, a first semiconductor layer being sandwiched between the semiconductor substrate and at least a portion of the bottom distant from the sidewall, and an insulating layer being sandwiched between the semiconductor substrate and the other portions of the bottom and/or the other portions of the sidewall. The present invention also provides a method for forming the semiconductor device. The present invention helps preventing the dopants in the source/drain regions from diffusing into the substrate.

摘要翻译： 本发明提供一种半导体器件，其形成在半导体衬底上，包括栅极堆叠，沟道区和源极/漏极区，其中栅极堆叠在沟道区上，沟道区位于半导体衬底中， 源极/漏极区域被嵌入在半导体衬底中，并且每个源极/漏极区域包括侧壁和底部，第二半导体层夹在沟道区域和远离底部的侧壁的一部分之间，第一 半导体层被夹在半导体衬底和远离侧壁的底部的至少一部分之间，绝缘层夹在半导体衬底和侧壁的底部和/或其它部分的其它部分之间。 本发明还提供了一种用于形成半导体器件的方法。 本发明有助于防止源/漏区中的掺杂剂扩散到衬底中。

公开(公告)号：US20120187491A1

公开(公告)日：2012-07-26

申请号：US13429948

申请日：2012-03-26

申请人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

IPC分类号： H01L29/772

CPC分类号： H01L21/187 ,  H01L21/6835 ,  H01L21/84 ,  H01L27/12 ,  H01L29/1083 ,  H01L2221/6835 ,  H01L2221/68368

摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.

摘要翻译： 提供一种形成电气装置的方法，包括在SOI衬底的第一半导体层上形成至少一个半导体器件。 形成接触至少一个半导体器件和第一半导体层的处理结构。 去除第二半导体层和SOI衬底的电介质层的至少一部分以提供第一半导体层的基本暴露的表面。 可以通过将掺杂剂通过第一半导体层的基本上暴露的表面注入从半导体层的基本暴露的表面延伸的半导体层的第一厚度来形成退化的阱，其中半导体层的剩余厚度基本上不含 的回归井掺杂剂。 退火井可以进行激光退火。

公开(公告)号：US20120168881A1

公开(公告)日：2012-07-05

申请号：US13142591

申请日：2011-01-27

申请人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 制造半导体器件的方法包括：提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽，所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽，其中所述第一介电层是拉伸应力介电层。 本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力，这提高了半导体器件的响应速度和性能。

公开(公告)号：US20120146103A1

公开(公告)日：2012-06-14

申请号：US13378206

申请日：2011-02-27

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/30608 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7849

摘要： The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.

摘要翻译： 本申请公开了半导体器件及其制造方法。 其中，所述半导体器件包括：半导体衬底; 嵌入在半导体衬底中的应力器; 设置在所述应力器上的通道区域; 设置在通道区域上的栅极堆叠; 源极/漏极区域，设置在沟道区域的两侧并且嵌入在半导体衬底中; 其中，所述应力器的表面包括顶壁，底壁和侧壁，所述侧壁包括第一侧壁和第二侧壁，所述第一侧壁连接所述顶壁和所述第二侧壁，所述第二侧 连接第一侧壁和底壁的壁，第一侧壁和第二侧壁之间的角度小于180°，第一侧壁和第二侧壁相对于平行于半导体的平面大致对称 基质。 本发明的实施例可应用于半导体器件制造中的应力工程技术。

公开(公告)号：US20120112252A1

公开(公告)日：2012-05-10

申请号：US13380380

申请日：2011-02-27

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor structure, which lies in covering a first dielectric layer with a second dielectric layer, forming a first contact hole with a small inner diameter within the second dielectric layer first, then etching the first dielectric layer to form a second contact hole with a much great inner diameter, and finally filling a conductive material into the first contact hole and the second contact hole to form contact plugs. Accordingly, the present invention further provides a semiconductor structure favorable for reducing contact resistance.

摘要翻译： 本发明提供了一种制造半导体结构的方法，该半导体结构覆盖第一介电层与第二介电层，首先在第二电介质层内形成具有小内径的第一接触孔，然后蚀刻第一介电层至 形成具有非常大的内径的第二接触孔，最后将导电材料填充到第一接触孔和第二接触孔中以形成接触塞。 因此，本发明还提供有利于降低接触电阻的半导体结构。