公开(公告)号：US08835316B2

公开(公告)日：2014-09-16

申请号：US13378997

申请日：2011-08-09

申请人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659

摘要： The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.

摘要翻译： 本发明提供一种晶体管，一种晶体管的制造方法和一种包括该晶体管的半导体芯片。 晶体管包括：有源区，栅极堆叠，初级间隔物和源/漏区，其中有源区在半导体衬底上; 栅极堆叠，初级间隔物和源极/漏极区域在有源区域上; 主要间隔物围绕栅极堆叠; 源极/漏极区域被嵌入有源区域中并且与主隔板的相对侧自对准。 其中，所述晶体管还包括：硅化物间隔物，其中所述硅化物间隔物位于所述主间隔物的相对侧，并且电介质材料填充在所述硅化物间隔物的所述栅堆叠的宽度方向的两端之间，以便 将源极/漏极区彼此隔离。

公开(公告)号：US20130009217A1

公开(公告)日：2013-01-10

申请号：US13378997

申请日：2011-08-09

申请人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659

摘要： It is provided a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. A method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack, a primary spacer, and source/drain regions, wherein the primary spacer surrounds the gate stack, and the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer; forming a semiconductor spacer surrounding the primary spacer, and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other; and covering the surfaces of the source/drain regions and the semiconductor spacer with a layer of metal or alloy, and annealing the resulting structure, so that a metal silicide is formed on the surfaces of the source/drain regions, and so that the semiconductor spacer is transformed into a silicide spacer simultaneously. As such, the risk of transistor failure due to atoms or ions of Ni entering the channel region through the source/drain extension regions is reduced.

摘要翻译： 提供晶体管，晶体管的制造方法和包括晶体管的半导体芯片。 一种用于制造晶体管的方法可以包括：在半导体衬底上限定有源区，以及在有源区上形成栅极堆叠，初级间隔物和源极/漏极区，其中主要间隔物包围栅极堆叠，源极 /漏极区域嵌入有源区域并与主间隔物的相对侧自对准; 形成围绕所述初级间隔物的半导体衬垫，并且在所述栅极叠层的宽度方向上切断所述半导体衬垫的端部，以将所述源极/漏极区彼此隔离; 并且用金属或合金层覆盖源极/漏极区域和半导体衬垫的表面，并对所得结构进行退火，使得在源极/漏极区域的表面上形成金属硅化物，并且使得半导体 间隔物同时转化成硅化物间隔物。 因此，由于通过源极/漏极延伸区域进入沟道区域的Ni的原子或离子导致的晶体管故障的风险降低。

公开(公告)号：US08822334B2

公开(公告)日：2014-09-02

申请号：US13380612

申请日：2011-04-18

申请人： Haizhou Yin ,  Jun Luo ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Jun Luo ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L21/44 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/66545

摘要： A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.

摘要翻译： 一种用于制造半导体结构的方法，包括：提供其上形成有虚拟栅极堆叠的衬底（100），在所述虚拟栅极堆叠的侧壁处形成间隔物（240），以及形成源/漏区（110）和 源极/漏极延伸区域（111）; 去除所述间隔物（240）的至少一部分，以暴露所述源极/漏极延伸区域（111）的至少一部分; 在源/漏区（110）和暴露的源极/漏极延伸区（111）上形成接触层（112），接触层（112）由CoSi2，NiSi和Ni（Pt）Si2 -y或其组合，并且接触层（112）的厚度小于10nm。 相应地，本发明还提供一种半导体结构，该半导体结构有利于降低接触电阻并且可以在随后的高温工艺中保持优异的性能。

公开(公告)号：US08642471B2

公开(公告)日：2014-02-04

申请号：US13379658

申请日：2011-02-27

申请人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L29/94

CPC分类号： H01L21/28518 ,  H01L21/28185 ,  H01L21/76814 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor structure. The method can effectively reduce the contact resistance between source/drain regions and a contact layer by forming two contact layers of different thickness on the surfaces of the source/drain regions. Further, the present invention provides a semiconductor structure, which has reduced the contact resistance.

摘要翻译： 本发明提供一种半导体结构的制造方法。 该方法可以通过在源极/漏极区域的表面上形成不同厚度的两个接触层来有效地降低源极/漏极区域和接触层之间的接触电阻。 此外，本发明提供一种降低了接触电阻的半导体结构。

公开(公告)号：US20120217589A1

公开(公告)日：2012-08-30

申请号：US13380612

申请日：2011-04-18

申请人： Haizhou Yin ,  Jun Luo ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Jun Luo ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/66545

摘要： A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.

摘要翻译： 一种用于制造半导体结构的方法，包括：提供其上形成有虚拟栅极堆叠的衬底（100），在所述虚拟栅极堆叠的侧壁处形成间隔物（240），以及形成源/漏区（110）和 源极/漏极延伸区域（111）; 去除所述间隔物（240）的至少一部分，以暴露所述源极/漏极延伸区域（111）的至少一部分; 在源/漏区（110）和暴露的源极/漏极延伸区（111）上形成接触层（112），接触层（112）由CoSi2，NiSi和Ni（Pt）Si2 -y或其组合，并且接触层（112）的厚度小于10nm。 相应地，本发明还提供一种半导体结构，该半导体结构有利于降低接触电阻并且可以在随后的高温工艺中保持优异的性能。

公开(公告)号：US20120205728A1

公开(公告)日：2012-08-16

申请号：US13379658

申请日：2011-02-27

申请人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28518 ,  H01L21/28185 ,  H01L21/76814 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, and forming a dummy gate stack on the substrate, sidewall spacers on sidewalls of the dummy gate stack, and source/drain regions at both sides of the dummy gate stack, wherein the dummy gate stack comprising a dummy gate; forming a first contact layer on surfaces of the source/drain regions; forming an interlayer dielectric layer to cover the first contact layer; removing the dummy gate or the dummy gate stack material to form an opening, filling the opening with a first conductive material or with a gate dielectric layer and a first conductive material to form a gate stack structure; forming through holes within the interlayer dielectric layer, so that a portion of the first contact layer or a portion of the first contact layer and the source/drain regions are exposed in the through holes; forming a second contact layer on the exposed portions of the regions; filling the through holes with a second conductive material to form contact vias. Besides, the present invention further provides a semiconductor structure, which is favorable for reducing the contact resistance.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括：提供衬底，在衬底上形成虚设栅极叠层，在虚拟栅极堆叠的侧壁上形成侧壁间隔物，以及虚拟栅极两侧的源极/漏极区域 堆叠，其中所述伪栅极堆叠包括虚拟栅极; 在所述源/漏区的表面上形成第一接触层; 形成层间电介质层以覆盖所述第一接触层; 去除伪栅极或虚拟栅极堆叠材料以形成开口，用第一导电材料或栅极电介质层和第一导电材料填充开口以形成栅极堆叠结构; 在所述层间电介质层内形成通孔，使得所述第一接触层的一部分或所述第一接触层的一部分和所述源/漏区在所述通孔中露出; 在所述区域的所述暴露部分上形成第二接触层; 用第二导电材料填充通孔以形成接触孔。 此外，本发明还提供了有利于降低接触电阻的半导体结构。

公开(公告)号：US08492206B2

公开(公告)日：2013-07-23

申请号：US13375692

申请日：2011-08-29

申请人： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

发明人： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

IPC分类号： H01L21/335 ,  H01L21/70

CPC分类号： H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

摘要： A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.

摘要翻译： 公开了一种半导体器件结构及其制造方法。 在一个实施例中，所述方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

公开(公告)号：US20130049125A1

公开(公告)日：2013-02-28

申请号：US13375692

申请日：2011-08-29

申请人： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

发明人： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

IPC分类号： H01L27/088 ,  H01L21/283

CPC分类号： H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

摘要： A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.

摘要翻译： 公开了一种半导体器件结构及其制造方法。 在一个实施例中，该方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

公开(公告)号：US08247278B2

公开(公告)日：2012-08-21

申请号：US13201109

申请日：2011-03-03

申请人： Huilong Zhu ,  Chunlong Li ,  Jun Luo

发明人： Huilong Zhu ,  Chunlong Li ,  Jun Luo

IPC分类号： H01L21/336

CPC分类号： H01L29/66795

摘要： The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance.

摘要翻译： 本申请公开了一种用于制造半导体器件的方法，包括以下步骤：在第一绝缘层上依次形成半导体衬底，栅极堆叠和第二保护层; 在限定栅极区域并且在栅极区域外部去除第二保护层和栅极堆叠的部分之后，同时将覆盖图案化半导体层的侧壁的半导体层，半导体层和第二绝缘层的部分保持在栅极区域外部 并暴露所述牺牲层，在所述半导体层中执行源/漏离子实现; 在形成第二侧壁间隔物以至少覆盖牺牲层的暴露部分之后，去除第一保护层和第二保护层以露出半导体层和栅极堆叠; 以及在所述半导体层和所述栅叠层的暴露部分上形成接触层; 进行平面化以使第一保护层露出，然后用第一侧壁间隔件和第二侧壁间隔件作为掩模去除第一保护层，牺牲层，停止层和半导体层，以形成空腔 其暴露第一绝缘层。 它有助于减少短沟道效应，源/漏区电阻和寄生电容。

公开(公告)号：US20120171833A1

公开(公告)日：2012-07-05

申请号：US13201109

申请日：2011-03-03

申请人： Huilong Zhu ,  Chunlong Li ,  Jun Luo

发明人： Huilong Zhu ,  Chunlong Li ,  Jun Luo

IPC分类号： H01L29/78

CPC分类号： H01L29/66795

摘要： The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance.

摘要翻译： 本申请公开了一种用于制造半导体器件的方法，包括以下步骤：在第一绝缘层上依次形成半导体衬底，栅极堆叠和第二保护层; 在限定栅极区域并且在栅极区域外部去除第二保护层和栅极堆叠的部分之后，同时将覆盖图案化半导体层的侧壁的半导体层，半导体层和第二绝缘层的部分保持在栅极区域外部 并暴露所述牺牲层，在所述半导体层中执行源/漏离子实现; 在形成第二侧壁间隔物以至少覆盖牺牲层的暴露部分之后，去除第一保护层和第二保护层以露出半导体层和栅极堆叠; 以及在所述半导体层和所述栅叠层的暴露部分上形成接触层; 进行平面化以使第一保护层露出，然后用第一侧壁间隔件和第二侧壁间隔件作为掩模去除第一保护层，牺牲层，停止层和半导体层，以形成空腔 其暴露第一绝缘层。 它有助于减少短沟道效应，源/漏区电阻和寄生电容。