公开(公告)号：US20140210511A1

公开(公告)日：2014-07-31

申请号：US13753856

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.

Abstract translation: 片上系统（SoC）具有耦合到一个或多个核心逻辑块的n行m列的非易失性存储器阵列。 M被限制为奇数。 每次写入一行m个数据位时，使用m个数据位来计算奇偶校验。 在存储奇偶校验位之前，它被反转。 每次读取一行时，检查奇偶校验以确定恢复的数据位中是否存在奇偶校验错误。 当检测到奇偶校验错误时，在SoC上执行引导操作。

公开(公告)号：US20140075233A1

公开(公告)日：2014-03-13

申请号：US13770448

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

Abstract translation: 处理设备的设计和操作可配置为在非易失性存储器恢复机器状态期间优化唤醒时间和峰值功耗成本。 处理装置包括被配置为存储由处理装置的多个易失性存储元件表示的机器状态的多个非易失性逻辑元件阵列。 将存储的机器状态从多个非易失性逻辑元件阵列读出到多个易失性存储元件。 在制造期间，非易失性逻辑元件阵列中每行的数行和数位数是基于目标唤醒时间和峰值功率成本的。 在另一种方法中，可以并行，顺序地或以任何组合来对数据进行数据写入或读取数据，以优化操作特性。

公开(公告)号：US20140075232A1

公开(公告)日：2014-03-13

申请号：US13769963

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/32

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.

Abstract translation: 检测处理装置的输入电源质量。 响应于检测到不良的电力质量，输入功率被断开，并且处理设备使用可用的存储电荷来备份非易失性逻辑单元阵列中的机器状态。 当电源恢复时，存储的机器状态从非易失性逻辑单元阵列恢复到易失性逻辑元件，由此处理设备从紧接在功率损耗之前的状态恢复其处理，允许跨间歇电源的无缝处理。