公开(公告)号：US5237528A

公开(公告)日：1993-08-17

申请号：US822325

申请日：1992-01-17

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： G11C11/404 ,  H01L27/10829 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。

公开(公告)号：US5214496A

公开(公告)日：1993-05-25

申请号：US452683

申请日：1989-12-19

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10829 ,  G11C11/404 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

公开(公告)号：US5140389A

公开(公告)日：1992-08-18

申请号：US475148

申请日：1990-02-05

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储电容器 要非常密集地布置的部分和足够大的电容以保持非常小的电池区域。 由于存储电容器部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的电容减小，因此存储器阵列噪声减小。 也可以设计电荷存储电容器部分，使得其一部分呈基本上垂直于衬底的壁的形式，以增加电容。

公开(公告)号：US5135097A

公开(公告)日：1992-08-04

申请号：US704928

申请日：1991-05-23

申请人： Chuichi Saito ,  Yoshio Sakai ,  Hideaki Takahashi ,  Kazuhira Ojima ,  Kazumi Kobune ,  Hisao Chiba

发明人： Chuichi Saito ,  Yoshio Sakai ,  Hideaki Takahashi ,  Kazuhira Ojima ,  Kazumi Kobune ,  Hisao Chiba

IPC分类号： B66B23/00 ,  B66B23/02 ,  B66B23/04 ,  B66B23/22

CPC分类号： B66B23/026 ,  B66B23/02 ,  B66B23/22

摘要： An escalator comprises a plurality of treadboards, coupled with each other in the endless form, for conveying people thereon, a driving device for driving the treadboards, which has a driving mechanism, including an electric motor, for transmitting a driving force from the motor to the treadboards and a power converting unit for supplying electric power to the motor. Component devices of the driving device are categorized into two groups in consideration of heat generated in the respective component devices. Component devices, which are categorized into a group of heat generating devices, are installed in a machine room, and component devices, which are categorized into a group of heat sensitive devices, are installed in another machine room. The two machine rooms are arranged in different locations within an escalator frame, which are remote from each other in the direction of the length of the frame.

摘要翻译： 自动扶梯包括多个以环形形式彼此联接的用于在其上传送人的踏板，用于驱动踏板的驱动装置，其具有包括电动机的驱动机构，用于将驱动力从电动机传递到 踏板和用于向马达供电的功率转换单元。 考虑到在各个组件装置中产生的热量，驱动装置的组件装置被分成两组。 分类为一组发热装置的部件装置安装在机房内，分类为一组热敏装置的部件装置安装在另一机房内。 这两个机房被安排在自动扶梯框架内的不同位置，它们在框架的长度方向上彼此远离。

公开(公告)号：US5132771A

公开(公告)日：1992-07-21

申请号：US503928

申请日：1990-04-04

申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

IPC分类号： G11C11/412 ,  H01L27/11

CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

公开(公告)号：US5028975A

公开(公告)日：1991-07-02

申请号：US527641

申请日：1990-05-23

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

公开(公告)号：US4907058A

公开(公告)日：1990-03-06

申请号：US214674

申请日：1988-07-01

申请人： Yoshio Sakai

发明人： Yoshio Sakai

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/0928 ,  H01L27/105

摘要： A CMOSLSI is disclosed which includes a semiconductor body, a first N-well region formed in the semiconductor body, a second N-well region, a greater part of which is formed in the first N-well region, a first P-well region formed in the semi-conductor body, a second P-well region, a greater part of which is formed in the first P-well region, a P-channel MOS transistor formed in the second N-well region, and an N-channel MOS transistor formed in the second P-well region, to reduce the distance between the P-channel MOS transistor and the N-channel MOS transistor, thereby increasing the packing density of the CMOSLSI.

摘要翻译： 公开了一种CMOSLSI，其包括半导体本体，形成在半导体本体中的第一N阱区，第二N阱区，其大部分形成在第一N阱区中，第一P阱区 形成在所述半导体体中的第二P阱区域，其大部分形成在所述第一P阱区域中，形成在所述第二N阱区域中的P沟道MOS晶体管和N沟道区域 MOS晶体管形成在第二P阱区中，以减小P沟道MOS晶体管和N沟道MOS晶体管之间的距离，从而增加CMOSLSI的堆积密度。

公开(公告)号：US4901128A

公开(公告)日：1990-02-13

申请号：US934556

申请日：1986-11-24

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： G11C11/404 ,  H01L27/10829 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。

公开(公告)号：US4853894A

公开(公告)日：1989-08-01

申请号：US71749

申请日：1987-07-09

申请人： Toshiaki Yamanaka ,  Norio Suzuki ,  Yoshio Sakai ,  Yoshifumi Kawamoto ,  Osamu Minato ,  Koichiro Ishibashi ,  Nobuyuki Moriwaki ,  Satoshi Meguro

发明人： Toshiaki Yamanaka ,  Norio Suzuki ,  Yoshio Sakai ,  Yoshifumi Kawamoto ,  Osamu Minato ,  Koichiro Ishibashi ,  Nobuyuki Moriwaki ,  Satoshi Meguro

IPC分类号： H01L27/06 ,  H01L21/3205 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/11

CPC分类号： H01L27/1112 ,  Y10S257/903

摘要： A semiconductor memory having static cells each composed of two driver MOS transistors formed on a semiconductor substrate and two transfer MOS transistors and two load resistors, which are formed on the substrate and are connected to the drains of the driver MOS transistors, respectively. A conductive film for fixing the sources of the driver MOS transistors to a ground voltage is formed above the principal surface of the semiconductor substrate, and this conductive film defines one electrode of a capacitance element formed on the substrate. The conductive film is formed over the load resistors formed on the semiconductor substrate so as to constitute an electric field shield for the load resistors.

摘要翻译： 一种具有静电单元的半导体存储器，分别由形成在半导体衬底上的两个驱动器MOS晶体管和两个传输MOS晶体管和两个负载电阻组成，分别形成在衬底上并连接到驱动器MOS晶体管的漏极。 在半导体衬底的主表面上形成用于将驱动器MOS晶体管的源极固定为接地电压的导电膜，该导电膜限定形成在衬底上的电容元件的一个电极。 导电膜形成在形成在半导体衬底上的负载电阻之上，以构成用于负载电阻器的电场屏蔽。

公开(公告)号：US4849801A

公开(公告)日：1989-07-18

申请号：US113381

申请日：1987-10-27

申请人： Shigeru Honjyo ,  Osamu Minato ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara

发明人： Shigeru Honjyo ,  Osamu Minato ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara

IPC分类号： H01L29/94 ,  G11C11/41 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/1112 ,  Y10S257/903

摘要： A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.

摘要翻译： 提供一种半导体存储器件，其中施加有电源电压或接地电压的电极设置在构成静态存储器件的存储单元的MOS晶体管的漏极和/或栅极上的绝缘层上，从而 增加存储单元的存储节点的电容。 该半导体存储器件显着地减少了软错误的发生。