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    Semiconductor memory device having flip-flop circuits
    6.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US5132771A

    公开(公告)日：1992-07-21

    申请号：US503928

    申请日：1990-04-04

    申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    IPC分类号： G11C11/412 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

    摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

    Method of fabricating stacked capacitor cell memory devices
    8.
    发明授权
    Method of fabricating stacked capacitor cell memory devices 失效
    叠层电容器单元存储器件的制造方法

    公开(公告)号：US5374576A

    公开(公告)日：1994-12-20

    申请号：US72482

    申请日：1993-06-03

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device having stacked capacitor cells
    9.
    发明授权
    Semiconductor memory device having stacked capacitor cells 失效
    具有层叠电容器单元的半导体存储器件

    公开(公告)号：US4970564A

    公开(公告)日：1990-11-13

    申请号：US287881

    申请日：1988-12-21

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10808

    摘要： A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45°的角度倾斜，使得存储容量 部分布置得非常密集和足够大的容量保持非常小的单元格区域。 此外，在半导体存储器件中，即使在位线上形成存储容量部分。 因此，位线被屏蔽，位线之间的电容减小，并且存储器阵列噪声降低。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4355374A

    公开(公告)日：1982-10-19

    申请号：US172378

    申请日：1980-07-24

    申请人： Yoshio Sakai ,  Mitsumasa Koyanagi ,  Hideo Sunami ,  Norikazu Hashimoto

    发明人： Yoshio Sakai ,  Mitsumasa Koyanagi ,  Hideo Sunami ,  Norikazu Hashimoto

    IPC分类号： G11C11/401 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  G11C11/40 ,  G11C11/24

    CPC分类号： G11C11/404 ,  H01L27/10805 ,  H01L27/10808

    摘要： A semiconductor memory comprising a memory cell disposed on a p-type semiconductor substrate and including an insulated-gate field effect transistor and a storage capacitor. The storage capacitor comprises: an insulator capacitor including a first electrode disposed on the substrate, a film of Si.sub.3 N.sub.4 disposed on the first electrode, and a second electrode disposed on the Si.sub.3 N.sub.4 film; and a pn junction capacitor including a first n-type impurity region for constituting either the source or drain of the insulated-gate field effect transistor, and a second p-type impurity region disposed in contact with the first impurity region and having a higher impurity concentration than the substrate.

    摘要翻译： 一种半导体存储器，包括设置在p型半导体衬底上并包括绝缘栅场效应晶体管和存储电容器的存储单元。 存储电容器包括：绝缘体电容器，包括设置在基板上的第一电极，设置在第一电极上的Si 3 N 4膜和设置在Si 3 N 4膜上的第二电极; 以及包含用于构成绝缘栅场效应晶体管的源极或漏极的第一n型杂质区和与第一杂质区接触并具有较高杂质的第二p型杂质区的pn结电容器 浓度比底物。