Abstract:
A method for allocating a physical hybrid ARQ indicator channel (PHICH) is disclosed. The method includes allocating a CDM group according to a cyclic prefix type in consideration of a ratio of the numbers of necessary CDM groups according to spreading factors, and allocating a PHICH to the allocated CDM group. The PHICH includes an ACK/NACK signal multiplexed by code division multiplexing (CDM). Therefore, resources for PHICH transmission are efficiently allocated and a transmission structure can be maintained irrespective of a spreading factor.
Abstract:
According to the present invention, it is possible to easily provide a polymeric macroparticle of which surface is modified with mesoparticles and nanoparticles, by the step of adhering mesoparticles and nanoparticles to the surface of said polymeric macroparticle to form a composite structure of nanoparticle-mesoparticle-macroparticle, and optionally subjecting to a heat treatment to fix said mesoparticles and nanoparticles onto the surface of macroparticle. In addition, a nanoparticle-polymer composite materials can be provide from the above polymeric macroparticles of which surface is modified with mesoparticles and nanoparticles.
Abstract:
A method of exchanging channel quality information between a base station and a user equipment in a mobile communication system is disclosed. A method of transmitting channel quality information in a mobile communication system which transmits channel quality information from a user equipment to a base station comprises transmitting channel quality information, which is measured based on a signal received from the base station, to the base station, receiving feedback information of the channel quality information from the base station, and transmitting difference information to the base station, the difference information for matching the channel quality information transmitted from the user equipment with channel quality information received by the base station based on the feedback information.
Abstract:
Disclosed herein are a probe and a method of making the same, and more particularly to a probe having a minute pitch, with which a probe card corresponding to arrangement of pads formed with a massed shape or other various shapes on a wafer is made, and a method of making the same. The probe having a prescribed thickness and formed in the shape of a flat plate. The probe comprises a body part bent at the middle thereof so that the body part is elastically tensioned or compressed when a tension force or a compression force is applied to the body part at the upper and lower ends thereof, a connection part integrally formed with the lower end of the body part, the connection part being fixed to a substrate, and a tip part integrally formed with the upper end of the body part, the tip part contacting a pad of an element.
Abstract:
The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.
Abstract:
A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
Abstract:
A method is provided for controlling a cache system. The cache system to be controlled comprises a direct-mapped cache configured with a small block size, and a fully associative spatial buffer configured with a large block, which includes a plurality of small blocks. Where accesses to the direct-mapped cache and the fully associative buffer are misses, data of a missed address and data of adjacent addresses are copied to the large block in the fully associative spatial buffer according to a first-in-first-out (FIFO) process. Furthermore, if one or more small data blocks is accessed among its corresponding large block of data which is to be expelled from the fully associative buffer, the small block(s) accessed is copied to the direct-mapped cache.
Abstract:
A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.
Abstract:
The present invention discloses a method for screening a sensing margin generated by a gate residue in a memory cell transistor. The method for screening failure of the memory cell transistor is summarized as follows. A test mode signal for sensing margin control is supplied. A write operation is performed to store data in the cell transistor. A word line is enabled by an active command. Isolated transistors disposed between a bit line coupled to the cell transistor and a bit line coupled to a sense amplifier are disabled to intercept a sensing operation. A voltage of the bit line coupled to the cell transistor is measured for a predetermined time. Here, voltage variations on the bit line are measured to screen failure of the cell transistor.