METHOD FOR ALLOCATING PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL
    111.
    发明申请
    METHOD FOR ALLOCATING PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL 有权
    用于分配物理混合自动重复请求指示器通道的方法

    公开(公告)号:US20090201904A1

    公开(公告)日:2009-08-13

    申请号:US12361185

    申请日:2009-01-28

    Abstract: A method for allocating a physical hybrid ARQ indicator channel (PHICH) is disclosed. The method includes allocating a CDM group according to a cyclic prefix type in consideration of a ratio of the numbers of necessary CDM groups according to spreading factors, and allocating a PHICH to the allocated CDM group. The PHICH includes an ACK/NACK signal multiplexed by code division multiplexing (CDM). Therefore, resources for PHICH transmission are efficiently allocated and a transmission structure can be maintained irrespective of a spreading factor.

    Abstract translation: 公开了一种用于分配物理混合ARQ指示符信道(PHICH)的方法。 该方法包括根据扩展因子考虑所需CDM组的数量的比例,根据循环前缀类型分配CDM组,并向所分配的CDM组分配PHICH。 PHICH包括通过码分复用(CDM)复用的ACK / NACK信号。 因此,有效地分配用于PHICH传输的资源,并且可以保持传输结构而不考虑扩频因子。

    POLYMER MACROPARTICLE OF WHICH SURFACE IS MODIFIED BY MESOPARTICLE AND NANOPARTICLE, NANOPARTICLE-POLYMER COMPOSITE USING THE SAME, AND PREPARATION THEREOF
    112.
    发明申请
    POLYMER MACROPARTICLE OF WHICH SURFACE IS MODIFIED BY MESOPARTICLE AND NANOPARTICLE, NANOPARTICLE-POLYMER COMPOSITE USING THE SAME, AND PREPARATION THEREOF 审中-公开
    由表面改性的聚合物大分子和纳米复合材料,使用该纳米复合材料的纳米聚合物复合材料及其制备方法

    公开(公告)号:US20090155592A1

    公开(公告)日:2009-06-18

    申请号:US12299836

    申请日:2007-05-07

    CPC classification number: C08K3/08 C08K3/22 Y10T428/2998 C08L67/02

    Abstract: According to the present invention, it is possible to easily provide a polymeric macroparticle of which surface is modified with mesoparticles and nanoparticles, by the step of adhering mesoparticles and nanoparticles to the surface of said polymeric macroparticle to form a composite structure of nanoparticle-mesoparticle-macroparticle, and optionally subjecting to a heat treatment to fix said mesoparticles and nanoparticles onto the surface of macroparticle. In addition, a nanoparticle-polymer composite materials can be provide from the above polymeric macroparticles of which surface is modified with mesoparticles and nanoparticles.

    Abstract translation: 根据本发明,通过将中等颗粒和纳米颗粒粘附到所述聚合物大颗粒的表面上,可以容易地提供表面用中间颗粒和纳米颗粒进行表面改性的聚合物大颗粒,以形成纳米颗粒 - 中微粒子的复合结构, 大颗粒,并且可选地进行热处理以将所述介晶和纳米颗粒固定在大颗粒的表面上。 此外,可以从其上表面用中间颗粒和纳米颗粒改性的上述聚合物大颗粒提供纳米颗粒 - 聚合物复合材料。

    PROBE AND METHOD OF MAKING SAME
    114.
    发明申请
    PROBE AND METHOD OF MAKING SAME 有权
    探索和制作方法

    公开(公告)号:US20080035487A1

    公开(公告)日:2008-02-14

    申请号:US11876180

    申请日:2007-10-22

    Abstract: Disclosed herein are a probe and a method of making the same, and more particularly to a probe having a minute pitch, with which a probe card corresponding to arrangement of pads formed with a massed shape or other various shapes on a wafer is made, and a method of making the same. The probe having a prescribed thickness and formed in the shape of a flat plate. The probe comprises a body part bent at the middle thereof so that the body part is elastically tensioned or compressed when a tension force or a compression force is applied to the body part at the upper and lower ends thereof, a connection part integrally formed with the lower end of the body part, the connection part being fixed to a substrate, and a tip part integrally formed with the upper end of the body part, the tip part contacting a pad of an element.

    Abstract translation: 本文公开了一种探针及其制造方法,更具体地说,涉及一种具有微小间距的探针,其中形成了与晶片上形成有组合形状或其它各种形状的焊盘布置对应的探针卡,以及 制作相同的方法。 探针具有规定的厚度并形成为平板状。 探头包括在其中间弯曲的主体部分,使得当在其上端和下端处对主体部分施加张力或压缩力时,主体部分被弹性张紧或压缩;与主体部分的上端和下端一体形成的连接部, 主体部分的下端,连接部分固定到基底,以及与主体部分的上端一体形成的尖端部分,尖端部分接触元件的垫。

    Non-volatile memory device and method of manufacturing the same
    115.
    发明申请
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号:US20070284648A1

    公开(公告)日:2007-12-13

    申请号:US11723222

    申请日:2007-03-19

    Abstract: The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.

    Abstract translation: 非易失性存储器件可以包括具有主体和一对翅片的半导体衬底。 桥式绝缘层可以非电连接该对翅片的上部,以限定一对翅片之间的空隙。 一对翅片的外表面是一对翅片的不面向空隙的表面,并且一对翅片的内表面是面对空隙的一对翅片的表面。 非易失性存储器件还可以包括至少一个可覆盖该对散热片的外表面的至少一部分的控制栅极电极,可以在该桥绝缘层上延伸,并且可以与该半导体衬底隔离。 至少一对栅极绝缘层可以在至少一个控制栅极电极和一对散热片之间,并且至少一对存储节点可以位于至少一对栅极绝缘层之间,并且至少一个控制 栅电极。

    Cache system and method for controlling the cache system comprising direct-mapped cache and fully-associative buffer
    118.
    发明授权
    Cache system and method for controlling the cache system comprising direct-mapped cache and fully-associative buffer 有权
    用于控制高速缓存系统的缓存系统和方法包括直接映射缓存和全关联缓冲器

    公开(公告)号:US07047362B2

    公开(公告)日:2006-05-16

    申请号:US10258074

    申请日:2001-05-16

    CPC classification number: G06F12/0897 G06F12/0864 Y02D10/13

    Abstract: A method is provided for controlling a cache system. The cache system to be controlled comprises a direct-mapped cache configured with a small block size, and a fully associative spatial buffer configured with a large block, which includes a plurality of small blocks. Where accesses to the direct-mapped cache and the fully associative buffer are misses, data of a missed address and data of adjacent addresses are copied to the large block in the fully associative spatial buffer according to a first-in-first-out (FIFO) process. Furthermore, if one or more small data blocks is accessed among its corresponding large block of data which is to be expelled from the fully associative buffer, the small block(s) accessed is copied to the direct-mapped cache.

    Abstract translation: 提供了一种用于控制高速缓存系统的方法。 要控制的缓存系统包括配置有小块大小的直接映射高速缓存器,以及配置有包括多个小块的大块的完全关联空间缓冲器。 在对直接映射高速缓存和完全关联缓冲区的访问丢失的情况下,根据先入先出(FIFO),将缺失地址的数据和相邻地址的数据复制到完全关联空间缓冲器中的大块 )过程。 此外,如果在要从全关联缓冲器中排出的相应的大量数据块之间访问一个或多个小数据块,则将所访问的小块复制到直接映射高速缓存。

    Translation look-aside buffer for improving performance and reducing power consumption of a memory and memory management method using the same
    119.
    发明授权
    Translation look-aside buffer for improving performance and reducing power consumption of a memory and memory management method using the same 失效
    翻译后备缓冲区,用于提高性能并降低内存的功耗以及使用其的内存管理方法

    公开(公告)号:US07024536B2

    公开(公告)日:2006-04-04

    申请号:US10253408

    申请日:2002-09-24

    Abstract: A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

    Abstract translation: 提供了能够降低功耗并提高存储器性能的翻译后备缓冲器(TLB)。 将虚拟地址转换为物理地址的全关联TLB包括具有多个存储体的第一TLB; 具有多个条目的第二TLB,每个条目具有一个虚拟页码和2个N个物理页号,其中N是自然数; 以及选择电路,用于响应于选择信号将第一TLB的输出信号输出到第二TLB,其中第一TLB的每个存储体具有多个条目,每个条目具有一个虚拟页码和一个物理页码 。 由第一TLB的虚拟页码指示的页面的大小与由第二TLB的虚拟页面编号指示的页面的大小不同。

    Method for screening failure of memory cell transistor
    120.
    发明授权
    Method for screening failure of memory cell transistor 有权
    屏蔽存储单元晶体管故障的方法

    公开(公告)号:US06999359B2

    公开(公告)日:2006-02-14

    申请号:US10850622

    申请日:2004-05-21

    CPC classification number: G11C29/50 G11C11/40

    Abstract: The present invention discloses a method for screening a sensing margin generated by a gate residue in a memory cell transistor. The method for screening failure of the memory cell transistor is summarized as follows. A test mode signal for sensing margin control is supplied. A write operation is performed to store data in the cell transistor. A word line is enabled by an active command. Isolated transistors disposed between a bit line coupled to the cell transistor and a bit line coupled to a sense amplifier are disabled to intercept a sensing operation. A voltage of the bit line coupled to the cell transistor is measured for a predetermined time. Here, voltage variations on the bit line are measured to screen failure of the cell transistor.

    Abstract translation: 本发明公开了一种用于筛选由存储单元晶体管中的栅极残留物产生的感测裕度的方法。 用于屏蔽存储单元晶体管故障的方法总结如下。 提供用于感测裕量控制的测试模式信号。 执行写入操作以将数据存储在单元晶体管中。 字线由有效命令启用。 设置在耦合到单元晶体管的位线和耦合到读出放大器的位线之间的隔离晶体管被禁止以截取感测操作。 耦合到单元晶体管的位线的电压被测量预定时间。 这里,测量位线上的电压变化以使单元晶体管的屏蔽故障。

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