公开(公告)号：US08547724B2

公开(公告)日：2013-10-01

申请号：US13032848

申请日：2011-02-23

Applicant: Yong-Jun Lee ,  Kwang Jin Lee ,  Joon Min Park ,  Huik Won Seo

Inventor： Yong-Jun Lee ,  Kwang Jin Lee ,  Joon Min Park ,  Huik Won Seo

IPC: G11C17/00

CPC classification number: G11C17/18 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0059 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

Abstract translation: 非易失性存储器件包括一次性可编程（OTP）锁定位寄存器。 非易失性存储器件包括可变电阻存储单元阵列，其包括存储数据的OTP块和存储指示数据是否可更改的OTP锁定状态信息的寄存器。 寄存器包括可变存储单元。 OTP锁定状态信息的初始值被设置为程序保护状态。

公开(公告)号：US20120307547A1

公开(公告)日：2012-12-06

申请号：US13364942

申请日：2012-02-02

Applicant: Joon Min Park ,  Kwang Jin Lee

Inventor： Joon Min Park ,  Kwang Jin Lee

IPC: G11C11/00

CPC classification number: G11C29/1201 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/18

Abstract: A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during a memory cell reset operation. The write driver is further configured to drive the selected bit line in sequence with a first set current pulse, which is responsive to the first external voltage, and a second set current pulse, which is responsive to a second external voltage input through a second terminal/pad of the memory device during a memory cell set operation.

Abstract translation: 非易失性存储器件包括电阻存储器单元阵列和写驱动器，其被配置为以复位电流脉冲驱动阵列中的选定位线，该复位电流脉冲响应于通过第一端子/ 存储器单元重置操作期间的存储器件。 所述写入驱动器被进一步配置为按照响应于所述第一外部电压的第一设定电流脉冲和第二设定电流脉冲依次驱动所选择的位线，所述第二设定电流脉冲响应于通过第二端子输入的第二外部电压 /存储器单元设置操作的焊盘。

公开(公告)号：US08250289B2

公开(公告)日：2012-08-21

申请号：US12402006

申请日：2009-03-11

Applicant: Yu-hwan Ro ,  Kwang-ho Kim ,  Kwang-jin Lee ,  Joon-yong Choi

Inventor： Yu-hwan Ro ,  Kwang-ho Kim ,  Kwang-jin Lee ,  Joon-yong Choi

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0223 ,  Y02D10/13

Abstract: A semiconductor memory device includes a memory cell array and the memory cell array includes: a plurality of memory blocks and at least one setting unit. The at least one setting unit stores a location and a size of a boot data storage region within the plurality of memory blocks that stores boot data. The at least one setting units may include a register for setting usage of each memory block as a boot block. The semiconductor device may be a phase-change memory.

Abstract translation: 半导体存储器件包括存储单元阵列，存储单元阵列包括：多个存储块和至少一个设置单元。 所述至少一个设置单元将存储引导数据的多个存储块内的引导数据存储区域的位置和大小存储起来。 至少一个设置单元可以包括用于将每个存储器块的使用设置为引导块的寄存器。 半导体器件可以是相变存储器。

公开(公告)号：US20120097601A1

公开(公告)日：2012-04-26

申请号：US13376124

申请日：2010-06-03

Applicant: Kwang Jin Lee ,  Moo-Seok Lee ,  Yong-Cheol Shin

Inventor： Kwang Jin Lee ,  Moo-Seok Lee ,  Yong-Cheol Shin

IPC: B01D63/02

CPC classification number: B01D63/022 ,  B01D63/021 ,  B01D2313/02 ,  B01D2313/21

Abstract: A hollow fiber membrane module is disclosed, which is capable of preventing a bundle of hollow fiber membranes from being separated from a module case, the hollow fiber membrane module for accommodating a bundle of hollow fiber membranes closely held together through the use of potting agent, including a module case including: a first inner surface serving as a projection on which the bundle of hollow fiber membranes is stably placed; a second inner surface upwardly extending from one end of the first inner surface, the second inner surface including at least one separation-preventing groove to prevent the bundle of hollow fiber membranes from being separated from the module case; a third inner surface downwardly extending from the other end of the first inner surface; and a fourth inner surface connected to the third inner surface.

Abstract translation: 公开了一种中空纤维膜组件，其能够防止一束中空纤维膜与模块壳体分离，中空纤维膜组件用于容纳通过使用灌封剂紧密地保持在一起的一束中空纤维膜， 包括模块壳体，包括：第一内表面，用作其上稳定放置中空纤维膜束的突起; 从所述第一内表面的一端向上延伸的第二内表面，所述第二内表面包括至少一个分离防止槽，以防止所述中空纤维束束与所述模块壳体分离; 从所述第一内表面的另一端向下延伸的第三内表面; 以及连接到第三内表面的第四内表面。

公开(公告)号：US20120090641A1

公开(公告)日：2012-04-19

申请号：US13265148

申请日：2010-04-19

Applicant: Kwang-Jin Lee

Inventor： Kwang-Jin Lee

IPC: B01D65/06 ,  B08B5/00 ,  B08B9/00 ,  B08B3/08

CPC classification number: B01D65/02 ,  B01D63/02 ,  B01D2315/06 ,  B01D2321/04 ,  B01D2321/162 ,  B01D2321/168 ,  B01D2321/185

Abstract: A method for cleaning a filtering membrane, contaminated by contaminants including inorganic and organic materials during a fluid-filtering process, is disclosed, the method comprises cleaning the filtering membrane by using a first cleaning solution of pH 6˜9 so as to remove the organic material from the filtering membrane; and cleaning the filtering membrane by using a second acid cleaning solution so as to remove the inorganic material from the filtering membrane, wherein the cleaning method of the present invention uses the first cleaning solution having pH 6˜9 instead of a strong-alkaline cleaning solution so as to prevent the filtering membrane from being damaged, and also uses the cleaning solution maintained at a a relatively low temperature instead of hot water so as to improve economical efficiency by reduction of energy consumption.

Abstract translation: 公开了一种在流体过滤过程中清洁被污染物包括无机和有机材料的过滤膜的方法，该方法包括使用pH6〜9的第一清洗液清洗过滤膜，以除去有机物 过滤膜材料; 并使用第二酸洗液清洗过滤膜，以从过滤膜中除去无机材料，其中本发明的清洗方法使用pH6〜9的第一清洗液代替强碱性清洗液 以防止过滤膜损坏，并且还使用保持在较低温度的清洗溶液代替热水，从而通过降低能量消耗来提高经济性。

公开(公告)号：US20110213922A1

公开(公告)日：2011-09-01

申请号：US13108143

申请日：2011-05-16

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

IPC: G06F12/02

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US20110209030A1

公开(公告)日：2011-08-25

申请号：US13099640

申请日：2011-05-03

Applicant: Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

Inventor： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

IPC: H03M13/05 ,  G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

Abstract: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

Abstract translation: 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

公开(公告)号：US20100302884A1

公开(公告)日：2010-12-02

申请号：US12662247

申请日：2010-04-07

Applicant: Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

Inventor： Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

IPC: G11C7/00

CPC classification number: G11C7/04 ,  G11C7/18 ,  G11C7/22 ,  G11C16/32 ,  G11C2207/002

Abstract: Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.

Abstract translation: 公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。 根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。 基于检查结果修改写操作信号。

公开(公告)号：US07751232B2

公开(公告)日：2010-07-06

申请号：US11953146

申请日：2007-12-10

Applicant: Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

Inventor： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC: G11C11/00

CPC classification number: G11C29/08 ,  G11C13/0004

Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

Abstract translation: 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US20100165729A1

公开(公告)日：2010-07-01

申请号：US12720918

申请日：2010-03-10

Applicant: Kwang-jin LEE ,  Choong-keun KWAK ,  Du-eung KIM

Inventor： Kwang-jin LEE ,  Choong-keun KWAK ,  Du-eung KIM

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

Abstract: In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

Abstract translation: 在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作 并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。