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    Resistance variable memory device for protecting coupling noise
    1.
    发明授权
    Resistance variable memory device for protecting coupling noise 有权
    用于保护耦合噪声的电阻可变存储器件

    公开(公告)号：US08310891B2

    公开(公告)日：2012-11-13

    申请号：US12574227

    申请日：2009-10-06

    Applicant: HoJung Kim ,  Joon-Yong Choi

    Inventor： HoJung Kim ,  Joon-Yong Choi

    IPC: G11C7/00

    CPC classification number: G11C13/004 ,  G11C7/02 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise.

    Abstract translation: 电阻变化存储装置技术领域本发明涉及一种电阻可变存储装置，更具体地，涉及一种能够防止耦合噪声影响的电阻变化存储装置。 电阻变化存储装置包括：连接到位线的存储单元; 预充电电路响应于预充电信号预充电所述位线; 偏置电路，响应于偏置信号向位线提供偏置电压; 以及控制逻辑来控制预充电信号和偏置信号。 控制逻辑以预充电间隔将偏置信号提供给偏置电路。 因此，根据本发明的电阻变化存储装置可以防止耦合噪声的影响。

    Nonvolatile memory device and method for controlling word line or bit line thereof
    2.
    发明授权
    Nonvolatile memory device and method for controlling word line or bit line thereof 有权
    用于控制字线或其位线的非易失性存储器件和方法

    公开(公告)号：US08305806B2

    公开(公告)日：2012-11-06

    申请号：US12659690

    申请日：2010-03-17

    Applicant: Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

    Inventor： Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

    IPC: G11C16/04

    CPC classification number: G11C16/08

    Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

    Abstract translation: 非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。 本地线分别对应于全局选择线。 第一选择电路被配置为连接到全局选择线以选择全局选择线。 第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。 第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

    Nonvolatile memory device using variable resistive element
    3.
    发明授权
    Nonvolatile memory device using variable resistive element 有权
    使用可变电阻元件的非易失性存储器件

    公开(公告)号：US08107275B2

    公开(公告)日：2012-01-31

    申请号：US12630484

    申请日：2009-12-03

    Applicant: Byung-Gil Choi ,  Joon-Yong Choi

    Inventor： Byung-Gil Choi ,  Joon-Yong Choi

    IPC: G11C11/00

    CPC classification number: G11C5/063 ,  G11C8/10 ,  G11C8/14 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2213/72

    Abstract: A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device includes first and second nonvolatile memory cells. Word lines are coupled to the first and second nonvolatile memory cells. First and second bit lines are coupled to the first and second nonvolatile memory cells, respectively. A read circuit reads resistance levels of the first and second nonvolatile memory cells by providing first and second read bias currents of different levels to the first and second bit lines, respectively.

    Abstract translation: 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件包括第一和第二非易失性存储单元。 字线耦合到第一和第二非易失性存储单元。 第一和第二位线分别耦合到第一和第二非易失性存储器单元。 读取电路通过分别向第一和第二位线提供不同电平的第一和第二读取偏置电流来读取第一和第二非易失性存储器单元的电阻电平。

    Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range
    4.
    发明授权
    Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range 有权
    相变存储器件和方法，其将相变材料的电阻保持在恒定电阻范围内的置位状态

    公开(公告)号：US07499306B2

    公开(公告)日：2009-03-03

    申请号：US11772569

    申请日：2007-07-02

    Applicant: Byung-gil Choi ,  Choong-keun Kwak ,  Sang-beom Kang ,  Joon-yong Choi

    Inventor： Byung-gil Choi ,  Choong-keun Kwak ,  Sang-beom Kang ,  Joon-yong Choi

    IPC: G11C11/00

    CPC classification number: G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2211/5647

    Abstract: Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

    Abstract translation: 提供一种将相变材料的电阻维持在恒定电阻范围内的置换状态的相变存储器件和方法。 在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二相位变换存储单元是否将数据 存储在第一相变存储单元中，提供给第一相变存储单元的数据相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元。

    PHASE-CHANGE MEMORY DEVICE AND METHOD THAT MAINTAINS THE RESISTANCE OF A PHASE-CHANGE MATERIAL IN A SET STATE WITHIN A CONSTANT RESISTANCE RANGE
    7.
    发明申请
    PHASE-CHANGE MEMORY DEVICE AND METHOD THAT MAINTAINS THE RESISTANCE OF A PHASE-CHANGE MATERIAL IN A SET STATE WITHIN A CONSTANT RESISTANCE RANGE 有权
    相变存储器件和在恒定电阻范围内保持相变材料在电阻状态下的电阻的方法

    公开(公告)号：US20080013362A1

    公开(公告)日：2008-01-17

    申请号：US11772569

    申请日：2007-07-02

    Applicant: Byung-gil Choi ,  Choong-keun Kwak ,  Sang-beom Kang ,  Joon-yong Choi

    Inventor： Byung-gil Choi ,  Choong-keun Kwak ,  Sang-beom Kang ,  Joon-yong Choi

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2211/5647

    Abstract: Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range; In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical; If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell;

    Abstract translation: 提供一种将相变材料的电阻维持在恒定电阻范围内的相变存储器件和方法， 在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二相位变换存储单元是否将数据 存储在第一相变存储单元中，提供给第一相变存储单元的数据相同; 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元;

    Nonvolatile memory using resistance material
    9.
    发明授权
    Nonvolatile memory using resistance material 有权
    使用电阻材料的非易失性存储器

    公开(公告)号：US07852666B2

    公开(公告)日：2010-12-14

    申请号：US12243578

    申请日：2008-10-01

    Applicant: Joon-Yong Choi ,  Byung-Gil Choi

    Inventor： Joon-Yong Choi ,  Byung-Gil Choi

    IPC: G11C11/00 ,  G11C8/00

    CPC classification number: G11C13/0069 ,  G11C7/18 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0078

    Abstract: A nonvolatile memory using a resistance material includes first and second memory-cell blocks having different block address information and each including a plurality of nonvolatile memory cells; a global bitline common to the first and second memory-cell blocks; first and second local bitlines corresponding to the first and second memory-cell blocks, respectively, and coupled to each other; and a common bitline selection circuit interposed between the first and second memory-cell blocks and coupled between the first and second local bitlines and the global bitline.

    Abstract translation: 使用电阻材料的非易失性存储器包括具有不同块地址信息并且各自包括多个非易失性存储单元的第一和第二存储单元块; 第一和第二存储单元块共同的全局位线; 分别对应于第一和第二存储单元块的第一和第二局部位线并彼此耦合; 以及插入在第一和第二存储单元块之间并耦合在第一和第二本地位线与全局位线之间的公共位线选择电路。

    Input circuit of a non-volatile semiconductor memory device
    10.
    发明授权
    Input circuit of a non-volatile semiconductor memory device 有权
    非易失性半导体存储器件的输入电路

    公开(公告)号：US07710791B2

    公开(公告)日：2010-05-04

    申请号：US11984145

    申请日：2007-11-14

    Applicant: Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    Inventor： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    IPC: G11C7/10 ,  G11C8/06 ,  G11C7/22 ,  G11C8/18

    CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C16/10

    Abstract: A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

    Abstract translation: 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

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