公开(公告)号：US20230094363A1

公开(公告)日：2023-03-30

申请号：US17952240

申请日：2022-09-24

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: H03M13/11 ,  H03M13/00

Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.

公开(公告)号：US20230006938A1

公开(公告)日：2023-01-05

申请号：US17745240

申请日：2022-05-16

Applicant: Microchip Technology Inc.

Inventor： Steven Scott GORSHE ,  Winston Mok

IPC: H04L47/25

Abstract: A system and method for performing rate adaptation and multiplexing of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of plurality of generic mapping procedure (GMP) thread frames for a respective stream of two or more streams of 64B/66B-encoded blocks of CR client data, defining a plurality of pseudo-Ethernet packets, mapping the plurality of GMP thread frames into consecutive pseudo-Ethernet packets, assembling a stream of GMP multiplexing frames comprising the consecutive pseudo-Ethernet packets, inserting a fixed number of idle blocks between the consecutive pseudo-Ethernet packets of the stream of GMP multiplexing frames and inserting an MTN path overhead (POH) frame into the stream of GMP multiplexing frames to generate a stream of GMP multiplexing rate adapted frames.

公开(公告)号：US20230006752A1

公开(公告)日：2023-01-05

申请号：US17745060

申请日：2022-05-16

Applicant: Microchip Technology Inc.

Inventor： Steven Scott GORSHE ,  Winston Mok

IPC: H04J3/16 ,  H04J3/07 ,  H04J3/12

Abstract: A system and method for performing rate adaptation of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of pseudo-Ethernet packets at a source node, assembling a plurality of Generic Mapping Procedure (GMP) frames by mapping a plurality of blocks from a stream of encoded blocks of CBR client data, a plurality of pad blocks, and GMP overhead into consecutive pseudo-Ethernet packets of the plurality of pseudo-Ethernet packets, inserting a fixed number of idle blocks between one or more of the consecutive pseudo-Ethernet packets and inserting an MTN path overhead (POH) frame that is aligned to the plurality of GMP frames to generate a plurality of rate adapted GMP frames for transmission over the MTN to an intermediate node or a sink node.

公开(公告)号：US11538726B2

公开(公告)日：2022-12-27

申请号：US17556790

申请日：2021-12-20

Applicant: Microchip Technology Inc.

Inventor： Matthias Klein ,  Andreas Zakrzewski ,  Richard Gruenwald

IPC: H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A method for forming a packaged electronic die includes forming a plurality of bonding pads on a device wafer. A photoresist layer is deposited over the device wafer and is patterned so as to form a photoresist frame that completely surrounds a device formed on the device wafer. Conductive balls are deposited over the bonding pads. The wafer is cut to form the electronic die and the electronic die is placed over the substrate. The conductive balls are heated and compressed, moving the electronic die closer to the substrate such that the photoresist frame is in direct contact with the substrate or with a landing pad formed on the substrate. Encapsulant material is deposited such that the encapsulant material covers the electronic die and the substrate. The encapsulant material is cured so as to encapsulate the electronic die. The substrate is cut to separate the packaged electronic die.

公开(公告)号：US20220382629A1

公开(公告)日：2022-12-01

申请号：US17825352

申请日：2022-05-26

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: G06F11/10

Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.

公开(公告)号：US11514994B1

公开(公告)日：2022-11-29

申请号：US17506735

申请日：2021-10-21

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  G11C11/54 ,  G11C29/50 ,  G11C29/10

Abstract: A method for outlier management at a flash controller includes testing a flash memory device to identify one or more outlier blocks of the flash memory device. Hyperparameters for a DNN are loaded into a training circuit of the flash controller. Test reads of the one or more outlier blocks are performed and a number of errors in the test reads is identified. The DNN is trained using a mini-batch training process and using the identified number of errors in the test reads and is tested to determine whether the trained DNN meets a training error threshold. The performing, the identifying, the training and the testing are repeated until the trained DNN meets the training error threshold to identify parameters of an outlier-block DNN. A neural network operation is performed using the identified parameters to predict a set of TVSO values. A read is performed using the set of predicted TVSO values.

公开(公告)号：US11514992B2

公开(公告)日：2022-11-29

申请号：US17234993

申请日：2021-04-20

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G11C16/34 ,  G06N5/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G06N3/04 ,  G06N3/063

Abstract: A method for reading a flash memory device includes storing configuration files of reliability-state Classification Neural Network (CNN) models and Regression Neural Network (RNN) inference models, and storing reliability-state tags corresponding to reliability states. The current number of P/E cycles is identified and a reliability-state CNN model is selected corresponding to the current number of P/E cycles. A neural network operation of the selected reliability-state CNN model is performed to identify a predicted reliability state. Corresponding reliability-state tags are identified and a corresponding RNN inference model is selected. A neural network operation of the selected RNN inference model is performed, using the reliability-state tags as input, to generate output indicating the shape of a threshold-voltage-shift read-error (TVS-RE) curve. Threshold Voltage Shift Offset (TVSO) values are identified corresponding to a minimum value of the TVS-RE curve and a read is performed using a threshold-voltage-shift read at the identified TVSO values.

公开(公告)号：US20220376693A1

公开(公告)日：2022-11-24

申请号：US17529522

申请日：2021-11-18

Applicant: Microchip Technology Inc.

Inventor： Jonathan W. Greene ,  Marcel Derevlean

IPC: H03K19/17728 ,  H03K19/21 ,  H03K19/17736

Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

公开(公告)号：US20220342590A1

公开(公告)日：2022-10-27

申请号：US17669995

申请日：2022-02-11

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F3/06

Abstract: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.

公开(公告)号：US20220300793A1

公开(公告)日：2022-09-22

申请号：US17480282

申请日：2021-09-21

Applicant: Microchip Technology Inc.

Inventor： Sathishkumar Donthu ,  Battu Prakash Reddy

IPC: G06N3/063 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: A method and apparatus for performing a convolution of a N×N matrix. A weights matrix for a N×N Convolutional Neural Network (CNN) is received and is divided into 3×3 weights matrixes. Lines of image values are read and are stored in a buffer as sets of image values. A 3×3 convolution is performed to generate a 3×3 convolution value. All 3×3 convolution values associated with a particular N×N convolution and a particular set of image values are summed. The 3×3 convolutions and the summing are repeated until all columns in the set of image values have been processed; and the reading, the storing, the performing 3×3 convolutions, the summing and the repeating performing 3×3 convolutions are repeated until all lines of image values have been processed. The sums associated with a particular N×N convolution are added together to generate an N×N convolution value for each of the N×N convolutions.