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117 条记录 (耗时 0.022 秒)

    Reduced potential generation circuit operable at low power-supply potential
    111.
    发明授权
    Reduced potential generation circuit operable at low power-supply potential 失效
    减少在低电源电位下工作的电位产生电路

    公开(公告)号：US06798276B2

    公开(公告)日：2004-09-28

    申请号：US10217408

    申请日：2002-08-14

    申请人： Katsuhiro Mori ,  Shinya Fujioka ,  Jun Ohno

    发明人： Katsuhiro Mori ,  Shinya Fujioka ,  Jun Ohno

    IPC分类号： G05F110

    CPC分类号： G05F3/262

    摘要： A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.

    摘要翻译： 电源电路包括将第一电位与第二电位进行比较的第一NMOS型电流镜电路和将第一电位与第三电位进行比较的第二NMOS型电流镜电路和调整第一电位的电位设定电路 响应于第一和第二NMOS型电流镜电路的输出的电位，使得第一电位落在第二电位和第三电位之间。

    Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless
    112.
    发明授权
    Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless 有权
    半导体存储装置进行后期写入操作并且控制测试读取操作以不是从数据锁存电路而是从存储器核心电路读取数据，而不管前面的地址和当前地址是否彼此匹配

    公开(公告)号：US06700816B2

    公开(公告)日：2004-03-02

    申请号：US10287495

    申请日：2002-11-05

    申请人： Yoshitaka Takahashi ,  Hitoshi Ikeda ,  Shinya Fujioka

    发明人： Yoshitaka Takahashi ,  Hitoshi Ikeda ,  Shinya Fujioka

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/00 ,  G11C8/06

    摘要： A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.

    摘要翻译： 半导体存储装置进行后期写入操作。 半导体存储装置包括：存储数据的存储器核心电路; 数据锁存电路，存储对应于先前的写入操作的先前数据; 比较与前一写入操作相对应的前一地址和对应于当前读操作的当前地址的地址比较电路，以便确定前一地址和当前地址是否彼此匹配; 和控制电路。 无论前一地址和当前地址是否彼此匹配，控制电路控制测试读取操作以从存储器核心电路读取数据。

    Semiconductor memory
    114.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US06324111B1

    公开(公告)日：2001-11-27

    申请号：US09561217

    申请日：2000-04-28

    申请人： Yasuharu Sato ,  Shinya Fujioka

    发明人： Yasuharu Sato ,  Shinya Fujioka

    IPC分类号： G11C702

    CPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/065

    摘要： A semiconductor memory includes p-type MOS transistors (11) dispersed in one-to-one correspondence with sense amplifiers (4−1-4−n) to activate their corresponding sense amplifiers, and a p-type MOS transistor (12) to activate the sense amplifiers (4−1-4−n). After the p-type MOS transistors (11) are overdriven by an external voltage (VCC) higher than a memory stored voltage, the p-type MOS transistor (12) is driven by an internal step-down voltage (VII) that is the memory stored voltage. This increases the driving capability per sense amplifier in comparison with a conventional method and further increases the speed of sense operation in comparison with a simple overdriving method.

    摘要翻译： 半导体存储器包括与读出放大器（4-1-4-n）一一对应地分散以激活其对应的读出放大器的p型MOS晶体管（11），以及p型MOS晶体管（12）， 激活读出放大器（4-1-4-n）。 在p型MOS晶体管（11）被高于存储器存储电压的外部电压（VCC）驱动之后，p型MOS晶体管（12）由内部降压电压（VII）驱动， 存储电压。 与传统方法相比，这增加了每个读出放大器的驱动能力，并且与简单的过驱动方法相比进一步增加了感测操作的速度。

    Integrated circuit device with input buffer capable of correspondence with highspeed clock
    115.
    发明授权
    Integrated circuit device with input buffer capable of correspondence with highspeed clock 有权
    具有与高速时钟对应的输入缓冲器的集成电路器件

    公开(公告)号：US06239631B1

    公开(公告)日：2001-05-29

    申请号：US09377104

    申请日：1999-08-19

    申请人： Shinya Fujioka ,  Hiroyoshi Tomita

    发明人： Shinya Fujioka ,  Hiroyoshi Tomita

    IPC分类号： H03L700

    CPC分类号： G11C7/1093 ,  G06F5/06 ,  G11C7/1087 ,  G11C7/222 ,  H03L7/00

    摘要： One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another. According to the present invention, the operation of input buffers of a plurality of sets are synchronized with internal clocks of a slower speed than a supplied clock, thus enabling the reliable receive of input signals.

    摘要翻译： 本发明的一个方面的特征在于，输入缓冲电路构成2组或相对于1个输入信号的多组，一对互补的内部时钟或多个内部时钟通过分频产生 集成电路器件内的提供的时钟和输入信号可以与一对互补时钟同步地接收和锁存，或者根据两组或多组的输入缓冲器与多个时钟同步地被接收和锁存。 2组或多组的输入缓冲器的输出由组合电路组合，并在内部提供。 为内部产生的内部时钟设置一个H电平或一个L电平周期，使得各种输入缓冲器的输出不会相互竞争。 根据本发明，多个组的输入缓冲器的操作与比所提供的时钟慢的内部时钟同步，因此能够可靠地接收输入信号。

    Semiconductor integrated circuit
    116.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US6091290A

    公开(公告)日：2000-07-18

    申请号：US910901

    申请日：1997-08-13

    申请人： Shinya Fujioka

    发明人： Shinya Fujioka

    IPC分类号： G11C11/407 ,  G01R31/30 ,  G11C11/401 ,  G11C29/06 ,  H03K5/08

    CPC分类号： G01R31/3004 ,  H03K5/08

    摘要： A semiconductor integrated circuit configured of a DRAM or the like has a function of generating a step-up voltage and supplying it to a plurality of semiconductor devices. During the period when a burn-in test is conducted, the input voltage of a precharge portion for precharging a step-up node for outputting the step-up voltage is clamped to a predetermined level by a precharge input voltage clamping unit. The precharge input voltage clamping unit prevents the step-up voltage level across the step-up node from excessively increasing during the burn-in test.

    摘要翻译： 由DRAM等构成的半导体集成电路具有产生升压电压并将其提供给多个半导体器件的功能。 在进行老化测试的期间中，用于将用于输出升压电压的升压节点预充电的预充电部分的输入电压通过预充电输入电压钳位单元钳位到预定电平。 预充电输入电压钳位单元防止升压节点的升压电压在老化测试期间过度增加。

    Synchronous semiconductor memory device and bus control method
    117.
    发明授权
    Synchronous semiconductor memory device and bus control method 有权
    同步半导体存储器件和总线控制方法

    公开(公告)号：US6084823A

    公开(公告)日：2000-07-04

    申请号：US323852

    申请日：1999-06-02

    申请人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

    发明人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/1072

    摘要： There is provided a semiconductor integrated circuit memory comprising banks each having at least one memory cell array and connected to a first data bus. Each of the banks includes a control part which is supplied with information indicated by a command and thus controls a data write or read operation on a corresponding bank. The control part controls data write and read operations on the corresponding bank so that the corresponding bank is prevented from occupying the first data bus until read data is output to the first data bus by the data read operation.

    摘要翻译： 提供了包括各自具有至少一个存储单元阵列并连接到第一数据总线的存储体的半导体集成电路存储器。 每个存储体包括控制部分，其被提供有由命令指示的信息，并且因此控制相应存储体上的数据写入或读取操作。 控制部分控制对应的存储体上的数据写入和读取操作，以便通过数据读取操作将读取数据输出到第一数据总线之前，防止对应的存储体占用第一数据总线。