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公开(公告)号：US20170048442A1
公开(公告)日：2017-02-16
申请号：US15237348
申请日：2016-08-15
Applicant: Apple Inc.
Inventor： Guy Cote , Garrett M. Johnson , James Edmund Orr, IV
CPC classification number: H04N5/2355 , G06T5/50 , G06T7/32 , G06T2207/10144 , G06T2207/10152 , G06T2207/20016 , G06T2207/20021 , G06T2207/20208 , H04N5/23216 , H04N5/23232 , H04N5/23245 , H04N5/23254 , H04N5/23258 , H04N5/2351 , H04N5/2352 , H04N5/2356 , H04N9/07
Abstract: Some embodiments provide a method of operating a device to capture an image of a high dynamic range (HDR) scene. Upon the device entering an HDR mode, the method captures and stores multiple images at a first image exposure level. Upon receiving a command to capture the HDR scene, the method captures a first image at a second image exposure level. The method selects a second image from the captured plurality of images. The method composites the first and second images to produce a composite image that captures the HDR scene. In some embodiments, the method captures multiple images at multiple different exposure levels.
Abstract translation: 一些实施例提供了一种操作设备以捕获高动态范围（HDR）场景的图像的方法。 当设备进入HDR模式时，该方法在第一图像曝光级别捕获并存储多个图像。 当接收到捕获HDR场景的命令时，该方法以第二图像曝光级别捕获第一图像。 该方法从所捕获的多个图像中选择第二图像。 该方法合成第一和第二图像以产生捕获HDR场景的合成图像。 在一些实施例中，该方法以多个不同的曝光水平捕获多个图像。
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公开(公告)号：US20160351138A1
公开(公告)日：2016-12-01
申请号：US14722620
申请日：2015-05-27
Applicant: Apple Inc.
Inventor： Chaohao Wang , Brijesh Tripathi , Christopher Philip Alan Tann , David S. Zalatimo , Guy Cote , Hao Nan , Marc Albrecht , Paolo Sacchetto , Sandro H. Pintz
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G2320/0204 , G09G2320/0247 , G09G2320/0257 , G09G2320/046 , G09G2340/0435 , G09G2360/16
Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.
Abstract translation: 电子设备可以产生要显示在显示器上的内容。 显示器可以具有用于显示内容的图像帧的液晶显示像素阵列。 可以以正极性和负极性显示图像帧以帮助减少电荷积累效应。 电荷累积跟踪器可以分析图像帧以确定何时存在电荷累积过多的风险。 电荷累积跟踪器可以分析关于灰度级，帧持续时间和帧极性的信息。 电荷积累跟踪器可以计算整个图像帧的电荷累积度量，或者可以分别处理每个帧的子区域。 当分区域被单独处理时，每个子区域可以被单独地监视以产生过量电荷累积的风险。
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公开(公告)号：US20160307298A1
公开(公告)日：2016-10-20
申请号：US14687513
申请日：2015-04-15
Applicant: Apple Inc.
Inventor： Jim C. Chou , Guy Cote , Haiyan He
CPC classification number: G06T3/4007 , G06T5/001 , G06T5/002 , G06T5/10 , G06T2207/10024 , G06T2207/20012 , G06T2207/20028 , G06T2207/20048
Abstract: An image signal processing system may include processing circuitry that may reduce banding artifacts in image data to be depicted on a display. The processing circuitry may receive a first pixel value associated with a first pixel of the image data and detect a first set of pixels located in a first direction along a same row of pixels or a same column of pixels with respect to the first pixel. The first set of pixels is associated with a first band. The processing circuitry may then interpolate a second pixel value based on an average of a first set of pixel values that correspond to the first set of pixels and a distance between the first pixel and a closest pixel in the first band. The processing circuitry may then output the second pixel value for the first pixel.
Abstract translation: 图像信号处理系统可以包括可以减少要在显示器上描绘的图像数据中的带状伪影的处理电路。 处理电路可以接收与图像数据的第一像素相关联的第一像素值，并且相对于第一像素沿同一行像素或相同列的像素检测位于第一方向上的第一组像素。 第一组像素与第一个带相关联。 然后，处理电路可以基于对应于第一组像素的第一组像素值的平均值和第一像素与第一像素中的最近像素之间的距离来内插第二像素值。 处理电路然后可以输出第一像素的第二像素值。
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公开(公告)号：US09472168B2
公开(公告)日：2016-10-18
申请号：US14201421
申请日：2014-03-07
Applicant: Apple Inc.
Inventor： Peter F. Holland , Guy Cote , Mark P. Rygh
CPC classification number: G09G5/39 , G09G5/001 , G09G5/022 , G09G5/363 , G09G2340/02 , G09G2340/06 , G09G2340/10 , G09G2340/12 , G09G2360/121 , G09G2360/128 , G09G2360/16
Abstract: In an embodiment, a system includes a display processing unit configured to process a video sequence for a target display. In some embodiments, the display processing unit is configured to composite the frames from frames of the video sequence and one or more other image sources. The display processing unit may be configured to write the processed/composited frames to memory, and may also be configured to generate statistics over the frame data, where the generated statistics are usable to encode the frame in a video encoder. The display processing unit may be configured to write the generated statistics to memory, and the video encoder may be configured to read the statistics and the frames. The video encoder may be configured to encode the frame responsive to the statistics.
Abstract translation: 在一个实施例中，系统包括被配置为处理用于目标显示的视频序列的显示处理单元。 在一些实施例中，显示处理单元被配置为从视频序列的帧和一个或多个其它图像源合成帧。 显示处理单元可以被配置为将经处理/合成的帧写入存储器，并且还可以被配置为生成关于帧数据的统计信息，其中生成的统计信息可用于对视频编码器中的帧进行编码。 显示处理单元可以被配置为将生成的统计信息写入存储器，并且视频编码器可以被配置为读取统计信息和帧。 视频编码器可以被配置为响应于统计信息对帧进行编码。
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公开(公告)号：US09344613B2
公开(公告)日：2016-05-17
申请号：US14171377
申请日：2014-02-03
Applicant: APPLE INC.
Inventor： Guy Cote , Jeffrey E. Frederiksen
CPC classification number: H04N5/2256 , H04N5/225 , H04N5/228 , H04N5/2354
Abstract: Certain aspects of this disclosure relate to an image signal processing system that includes a flash controller that is configured to activate a flash device prior to the start of a target image frame by using a sensor timing signal. In one embodiment, the flash controller receives a delayed sensor timing signal and determines a flash activation start time by using the delayed sensor timing signal to identify a time corresponding to the end of the previous frame, increasing that time by a vertical blanking time, and then subtracting a first offset to compensate for delay between the sensor timing signal and the delayed sensor timing signal. Then, the flash controller subtracts a second offset to determine the flash activation time, thus ensuring that the flash is activated prior to receiving the first pixel of the target frame.
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Patent Agency Ranking
公开(公告)号：US09224186B2
公开(公告)日：2015-12-29
申请号：US14039804
申请日：2013-09-27
Applicant: Apple Inc.
Inventor： Mark P. Rygh , Guy Cote , Timothy John Millet , Joseph J. Cheng
IPC: G06T1/20 , G06T1/60 , H04N19/423 , H04N19/436 , H04N19/176
CPC classification number: G06T1/20 , G06T1/60 , H04N19/176 , H04N19/423 , H04N19/436 , H04N19/523 , H04N19/593
Abstract: Memory latency tolerance methods and apparatus for maintaining an overall level of performance in block processing pipelines that prefetch reference data into a search window. In a general memory latency tolerance method, search window processing in the pipeline may be monitored. If status of search window processing changes in a way that affects pipeline throughput, then pipeline processing may be modified. The modification may be performed according to no stall methods, stall recovery methods, and/or stall prevention methods. In no stall methods, a block may be processed using the data present in the search window without waiting for the missing reference data. In stall recovery methods, the pipeline is allowed to stall, and processing is modified for subsequent blocks to speed up the pipeline and catch up in throughput. In stall prevention methods, processing is adjusted in advance of the pipeline encountering a stall condition.
Abstract translation: 存储器延迟容限方法和装置，用于在预处理参考数据到搜索窗口的块处理管线中维持整体性能水平。 在通用存储器延迟容限方法中，可以监视流水线中的搜索窗口处理。 如果搜索窗口处理的状态以影响流水线吞吐量的方式改变，则可以修改流水线处理。 修改可以根据没有失速方法，失速恢复方法和/或失速预防方法进行。 在没有停止方法的情况下，可以使用搜索窗口中存在的数据来处理块，而不用等待丢失的参考数据。 在失速恢复方法中，允许管道停止，并且修改后续块的处理以加速管道并追赶吞吐量。 在失速预防方法中，在遇到失速状况的管道之前调整处理。
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公开(公告)号：US09215472B2
公开(公告)日：2015-12-15
申请号：US14039729
申请日：2013-09-27
Applicant: Apple Inc.
Inventor： James E. Orr , Timothy John Millet , Joseph J. Cheng , Nitin Bhargava , Guy Cote
IPC: G06T1/20 , G06T1/00 , G06F15/00 , H04N19/43 , H04N19/433 , H04N19/436 , H04N19/51 , H04N19/583 , H04N19/513
CPC classification number: H04N19/43 , G06T1/20 , H04N19/433 , H04N19/436 , H04N19/51 , H04N19/513
Abstract: A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.
Abstract translation: 一个块处理流水线，包括一个软件流水线和并行运行的硬件流水线。 软件管道在硬件管道之前至少运行一个程序段。 流水线的各个阶段可以各自包括在该阶段对当前块执行一个或多个操作的硬件流水线组件。 管道的至少一个阶段还可以包括软件流水线组件，该软件流水线组件在硬件组件正在处理当前块时，在流水线阶段确定用于处理下一个块的硬件组件的配置。 软件管线组件可以根据从流水线的上游级获得的与下一块相关的信息来确定配置。 软件管道组件还可以获得并使用与先前在该阶段处理的块相关的信息。
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公开(公告)号：US20150249833A1
公开(公告)日：2015-09-03
申请号：US14503200
申请日：2014-09-30
Applicant: Apple Inc.
Inventor： Alexandros Tourapis , David Singer , Guy Cote , Timothy J. Millet
IPC: H04N19/154 , H04N19/124 , H04N19/40 , H04N19/176 , H04N19/103 , H04N19/196
CPC classification number: H04N19/154 , H04N19/103 , H04N19/124 , H04N19/176 , H04N19/196 , H04N19/40
Abstract: Embodiments of the present invention may provide a video coder. The video coder may include an encoder to perform coding operations on a video signal in a first format to generate coded video data, and a decoder to decode the coded video data. The video coder may also include an inverse format converter to convert the decoded video data to second format that is different than the first format and an estimator to generate a distortion metric using the decoded video data in the second format and the video signal in the second format. The encoder may adjust the coding operations based on the distortion metric.
Abstract translation: 本发明的实施例可以提供视频编码器。 视频编码器可以包括编码器，以对第一格式的视频信号执行编码操作，以产生编码的视频数据，以及解码器，对编码的视频数据进行解码。 视频编码器还可以包括逆格式转换器，用于将解码的视频数据转换为与第一格式不同的第二格式，以及估计器，以使用第二格式的解码视频数据和第二格式的视频信号来生成失真度量 格式。 编码器可以基于失真度量来调整编码操作。
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公开(公告)号：US20150091914A1
公开(公告)日：2015-04-02
申请号：US14039820
申请日：2013-09-27
Applicant: Apple Inc.
Inventor： Guy Cote , Mark P. Rygh , Timothy John Millet , Jim C. Chou , Joseph J. Cheng
IPC: G06T1/20
CPC classification number: G06T1/20 , H04N19/423 , H04N19/436 , H04N19/61
Abstract: A knight's order processing method for block processing pipelines in which the next block input to the pipeline is taken from the row below and one or more columns to the left in the frame. The knight's order method may provide spacing between adjacent blocks in the pipeline to facilitate feedback of data from a downstream stage to an upstream stage. The rows of blocks in the input frame may be divided into sets of rows that constrain the knight's order method to maintain locality of neighbor block data. Invalid blocks may be input to the pipeline at the left of the first set of rows and at the right of the last set of rows, and the sets of rows may be treated as if they are horizontally arranged rather than vertically arranged, to maintain continuity of the knight's order algorithm.
Abstract translation: 一种用于块处理管线的骑士订单处理方法，其中从管线的下一个块输入下一个块，并且在该帧中从左侧获取一个或多个列。 骑士的订单方法可以在管道中的相邻块之间提供间隔，以便于数据从下游阶段到上游阶段的反馈。 输入帧中的块行可以被划分为限制骑士命令方法以维持相邻块数据的位置的行的集合。 无效的块可以被输入到第一组行的左侧和最后一组行的右侧的流水线，并且这些行的集合可以被视为水平排列而不是垂直排列，以保持连续性 的骑士秩序算法。
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公开(公告)号：US20150085931A1
公开(公告)日：2015-03-26
申请号：US14037310
申请日：2013-09-25
Applicant: Apple Inc.
Inventor： Guy Cote , Craig M. Okruhlica
IPC: H04N19/42 , H04N19/583
CPC classification number: H04N19/186 , H04N19/107 , H04N19/13 , H04N19/159 , H04N19/176 , H04N19/182 , H04N19/40 , H04N19/423 , H04N19/436 , H04N19/439 , H04N19/52 , H04N19/593 , H04N19/86 , H04N19/96
Abstract: A block processing pipeline in which macroblocks are input to and processed according to row groups so that adjacent macroblocks on a row are not concurrently at adjacent stages of the pipeline. The input method may allow chroma processing to be postponed until after luma processing. One or more upstream stages of the pipeline may process luma elements of each macroblock to generate luma results such as a best mode for processing the luma elements. Luma results may be provided to one or more downstream stages of the pipeline that process chroma elements of each macroblock. The luma results may be used to determine processing of the chroma elements. For example, if the best mode for luma is an intra-frame mode, then a chroma processing stage may determine a best intra-frame mode for chroma and reconstruct the chroma elements according to the best chroma intra-frame mode.
Abstract translation: 块处理流水线，其中宏块被输入到并根据行组进行处理，使得一行上的相邻宏块不是在流水线的相邻阶段同时进行。 输入法可以允许色度处理被推迟直到亮度处理。 流水线的一个或多个上游级可以处理每个宏块的亮度元素以产生亮度结果，例如用于处理亮度元素的最佳模式。 亮度结果可以被提供给处理每个宏块的色度元素的流水线的一个或多个下游阶段。 亮度结果可用于确定色度元素的处理。 例如，如果亮度的最佳模式是帧内模式，则色度处理阶段可以确定用于色度的最佳帧内模式，并且根据最佳色度帧内模式重建色度元素。
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