公开(公告)号：US20210287344A1

公开(公告)日：2021-09-16

申请号：US17331602

申请日：2021-05-26

Applicant: Apple Inc.

Inventor： Jim C. Chou ,  Yun Gong

IPC: G06T5/00 ,  G06T3/40 ,  G06T5/50

Abstract: An electronic device may include scaling circuitry to scale input pixel data to a greater resolution. The directional scaling circuitry may include first interpolation circuitry to receive best mode data, including one or more angles corresponding to content of the image and interpolate first pixel values at first pixel positions diagonally offset from input pixel positions of the input pixel data based on the best mode data and input pixel values corresponding to the input pixel positions. The directional scaling circuitry may also include second interpolation circuitry to receive the best mode data and the input pixel values and interpolate second pixel values at second pixel positions horizontally or vertically offset from the input pixel positions based at least in part on the best mode data and the input pixel values.

公开(公告)号：US10757437B2

公开(公告)日：2020-08-25

申请号：US14334614

申请日：2014-07-17

Applicant: Apple Inc.

Inventor： Jim C. Chou ,  Mark P. Rygh

IPC: H04N19/513 ,  H04N19/433 ,  H04N19/53 ,  H04N19/523 ,  H04N19/533

Abstract: Block processing pipeline methods and apparatus in which. motion estimation is performed at a stage of a motion estimation module for a current block with respect to a reference frame at one or more partition sizes to determine candidate motion vectors. The candidate motion vectors may be passed to a next stage for refinement. Motion estimation may then be performed at the next stage to refine the motion vectors. In performing motion estimation at this stage, the input motion vectors of at least one partition size received from the previous stage may be used as candidate motion vectors in searches for at least one other partition size.

公开(公告)号：US20180091827A1

公开(公告)日：2018-03-29

申请号：US15274045

申请日：2016-09-23

Applicant: Apple Inc.

Inventor： Jim C. Chou ,  Syed Muhammad A. Rizvi

IPC: H04N19/91 ,  H04N19/184 ,  H04N19/13 ,  H04N19/40 ,  H04N19/50

Abstract: Systems and methods for improving determination of encoded image data using a video encoding pipeline, which includes a first transcode engine that entropy encodes a first portion of a bin stream to determine a first bit stream including first encoded image data that indicates a first coding group row and that determines first characteristic data corresponding to the first bit stream to facilitate communicating a combined bit stream; and a second transcode engine that entropy encode a second portion of the bin stream to determine a second bit stream including second encoded image data that indicates a second coding group row while the first transcode engine entropy encodes the first portion of the bin stream and that determines second characteristic data corresponding to the second bit stream to facilitate communicating the combined bit stream, which includes the first bit stream and the second bit stream, to a decoding device.

公开(公告)号：US20170094300A1

公开(公告)日：2017-03-30

申请号：US15087760

申请日：2016-03-31

Applicant: APPLE INC.

Inventor： Jim C. Chou ,  Syed Muhammad Ali Rizvi ,  Weichun Ku

IPC: H04N19/50 ,  H04N19/40 ,  H04N19/91 ,  H04N19/70

CPC classification number: H04N19/50 ,  H04N19/436 ,  H04N19/91

Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes a transcode pipeline that provides entropy encoding of binarized syntax elements. More specifically, multiple bins may be encoded in parallel, resulting in increased encoding throughput.

公开(公告)号：US20170094284A1

公开(公告)日：2017-03-30

申请号：US14871797

申请日：2015-09-30

Applicant: Apple Inc.

Inventor： Jim C. Chou ,  Weichun Ku

IPC: H04N19/147 ,  H04N19/593 ,  H04N19/635 ,  H04N19/567 ,  H04N19/583 ,  H04N19/503 ,  H04N19/513

CPC classification number: H04N19/147 ,  H04N19/103 ,  H04N19/176 ,  H04N19/503 ,  H04N19/513 ,  H04N19/53 ,  H04N19/567 ,  H04N19/583 ,  H04N19/593 ,  H04N19/635 ,  H04N19/70 ,  H04N19/86 ,  H04N19/91

Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes bit-rate statistics generation that is useful for controlling subsequent bit rates and/or determining encoding operational modes.

公开(公告)号：US09473778B2

公开(公告)日：2016-10-18

申请号：US14039871

申请日：2013-09-27

Applicant: Apple Inc.

Inventor： Jim C. Chou ,  Craig M. Okruhlica ,  Guy Cote

IPC: H04N7/26 ,  H04N19/17 ,  H04N19/105 ,  H04N19/147 ,  H04N19/192 ,  H04N19/176 ,  H04N19/186

CPC classification number: H04N19/17 ,  H04N19/105 ,  H04N19/147 ,  H04N19/176 ,  H04N19/186 ,  H04N19/192

Abstract: The video encoders described herein may make an initial determination to designate a macroblock as a skip macroblock, but may subsequently reverse that decision based on additional information. For example, an initial skip mode decision may be based on aggregate distortion metrics for the luma component of the macroblock (e.g., SAD, SATD, or SSD), then reversed based on an individual pixel difference metric, an aggregate or individual pixel metric for a chroma component of the macroblock, or on the position of the macroblock within a macroblock row. The final skip mode decision may be based, at least in part, on the maximum difference between any pixel in the macroblock (or in a region of interest within the macroblock) and the corresponding pixel in a reference frame. The initial skip mode decision may be made during an early stage of a pipelined video encoding process and reversed in a later stage.

Abstract translation: 本文描述的视频编码器可以进行初始确定以将宏块指定为跳过宏块，但是随后可以基于附加信息来反转该决定。 例如，初始跳过模式决定可以基于宏块的亮度分量（例如，SAD，SATD或SSD）的聚合失真度量，然后基于单独的像素差异度量来反转，聚合或单独的像素度量用于 宏块的色度分量，或宏块行内宏块的位置。 至少部分地，最终跳过模式决定基于宏块中的任何像素（或宏块内的感兴趣区域）与参考帧中的相应像素之间的最大差异。 初始跳过模式决定可以在流水线视频编码处理的早期阶段进行，并且在稍后的阶段中反转。

公开(公告)号：US09392292B2

公开(公告)日：2016-07-12

申请号：US14039880

申请日：2013-09-27

Applicant: Apple Inc.

Inventor： Weichun Ku ,  Jim C. Chou

IPC: H04N19/13 ,  H04N19/70 ,  H04N19/103 ,  H04N19/176 ,  H04N19/129 ,  H04N19/463 ,  H04N19/40 ,  H04N19/42

CPC classification number: H04N19/176 ,  H04N19/129 ,  H04N19/13 ,  H04N19/40 ,  H04N19/439 ,  H04N19/463

Abstract: A video encoder may include a context-adaptive binary arithmetic coding (CABAC) encode component that converts each syntax element of a representation of a block of pixels to binary code, serializes it, and codes it mathematically with its probability model, after which the resulting bit stream is output. When the probability of a bin being coded with one of two possible symbols is one-half, the bin may be coded using bypass bin coding mode rather than a more compute-intensive regular bin coding mode. The CABAC encoder may code multiple consecutive bypass bins in a series of cascaded processing units during a single processing cycle (e.g., a regular bin coding cycle). Intermediate outputs of each processing unit may be coupled to inputs of the next processing unit. A resolver unit may accept intermediate outputs of the processing units and generate final output bits for the bypass bins.

Abstract translation: 视频编码器可以包括上下文自适应二进制算术编码（CABAC）编码组件，其将像素块的表示的每个语法元素转换为二进制码，将其序列化，并用其概率模型对其进行数学编码，之后得到 输出位流。 当用两个可能符号中的一个编码一个bin的概率为一半时，可以使用旁路箱编码模式而不是更计算密集的常规二进制编码模式对该bin进行编码。 CABAC编码器可以在单个处理周期（例如，常规bin编码周期）期间对一系列级联处理单元中的多个连续旁路仓进行编码。 每个处理单元的中间输出可以耦合到下一处理单元的输入。 解算器单元可以接收处理单元的中间输出并且产生旁路箱的最终输出位。

公开(公告)号：US09351003B2

公开(公告)日：2016-05-24

申请号：US14039900

申请日：2013-09-27

Applicant: Apple Inc.

Inventor： Guy Cote ,  Weichun Ku ,  Jim C. Chou

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/423 ,  H04N19/70 ,  H04N19/129 ,  H04N19/463 ,  H04N19/436 ,  H04N19/40

CPC classification number: H04N19/13 ,  H04N19/129 ,  H04N19/176 ,  H04N19/40 ,  H04N19/423 ,  H04N19/436 ,  H04N19/463 ,  H04N19/70

Abstract: A video encoder may include a context-adaptive binary arithmetic coding (CABAC) encode component that converts each syntax element of a representation of a block of pixels to binary code, serializes it, and codes it mathematically, after which the resulting bit stream is output. A lookup table in memory and a context cache may store probability values for supported contexts, which may be retrieved from the table or cache for use in coding syntax elements. Depending on the results of a syntax element coding, the probability value for its context may be modified (e.g., increased or decreased) in the cache and, subsequently, in the table. After coding multiple syntax elements, and based on observed access patterns for probability values, a mapping or indexing for the cache or the table may be modified to improve cache performance (e.g., to reduce cache misses or access data for related contexts using fewer accesses).

Abstract translation: 视频编码器可以包括上下文自适应二进制算术编码（CABAC）编码组件，其将像素块的表示的每个语法元素转换成二进制码，将其串行化并对其进行数学编码，之后输出所得到的比特流 。 存储器和上下文高速缓存中的查找表可以存储支持的上下文的概率值，其可以从表或高速缓存中检索以用于编码语法元素。 取决于语法元素编码的结果，其上下文的概率值可以在高速缓存中以及随后的表中被修改（例如增加或减少）。 在编码多个语法元素之后，并且基于观察到的概率值的访问模式，可以修改高速缓存或表的映射或索引以提高缓存性能（例如，减少高速缓存未命中或使用较少访问来访问相关上下文的数据） 。

公开(公告)号：US09336558B2

公开(公告)日：2016-05-10

申请号：US14039845

申请日：2013-09-27

Applicant: Apple Inc.

Inventor： Guy Cote ,  Timothy John Millet ,  Joseph J. Cheng ,  Mark P. Rygh ,  Jim C. Chou

IPC: H04N19/436 ,  G06T1/20 ,  H04N19/176 ,  G06T1/60 ,  H04N19/423

CPC classification number: G06T1/20 ,  G06T1/60 ,  H04N19/176 ,  H04N19/40 ,  H04N19/423 ,  H04N19/436 ,  H04N19/91

Abstract: In the video encoders described herein, blocks of pixels from a video frame may be encoded (e.g., using CAVLC encoding) in a block processing pipeline using wavefront ordering (e.g., in knight's order). Each of the encoded blocks may be written to a particular one of multiple DMA buffers such that the encoded blocks written to each of the buffers represent consecutive blocks of the video frame in scan order. A transcode pipeline may operate in parallel with (or at least overlapping) the operation of the block processing pipeline. The transcode pipeline may read encoded blocks from the buffers in scan order and merge them into a single bit stream (in scan order). A transcoder core of the transcode pipeline may decode the encoded blocks and encode them using a different encoding process (e.g., CABAC). In some cases, the transcoder may be bypassed.

Abstract translation: 在本文描述的视频编码器中，来自视频帧的像素块可以使用波前排序（例如骑士顺序）在块处理流水线中进行编码（例如，使用CAVLC编码）。 每个编码块可以被写入多个DMA缓冲器中的特定一个，使得写入每个缓冲器的编码块以扫描顺序表示视频帧的连续块。 代码流水线可以与（或至少重叠）块处理流水线的操作并行操作。 代码流水线可以以扫描顺序从缓冲器读取编码块，并将它们合并成单个位流（按扫描顺序）。 代码转换流水线的代码转换器核心可以解码编码的块，并使用不同的编码过程（例如，CABAC）对它们进行编码。 在某些情况下，代码转换器可能被旁路。

公开(公告)号：US20160021385A1

公开(公告)日：2016-01-21

申请号：US14334614

申请日：2014-07-17

Applicant: Apple Inc.

Inventor： Jim C. Chou ,  Mark P. Rygh

IPC: H04N19/513

CPC classification number: H04N19/513 ,  H04N19/433 ,  H04N19/523 ,  H04N19/53 ,  H04N19/533

Abstract: Block processing pipeline methods and apparatus in which. motion estimation is performed at a stage of a motion estimation module for a current block with respect to a reference frame at one or more partition sizes to determine candidate motion vectors. The candidate motion vectors may be passed to a next stage for refinement. Motion estimation may then be performed at the next stage to refine the motion vectors. In performing motion estimation at this stage, the input motion vectors of at least one partition size received from the previous stage may be used as candidate motion vectors in searches for at least one other partition size.

Abstract translation: 块处理管道的方法和装置。 在针对当前块的运动估计模块的阶段，对于一个或多个分区大小的参考帧执行运动估计，以确定候选运动矢量。 可以将候选运动矢量传递到下一阶段以进行细化。 然后可以在下一阶段执行运动估计，以细化运动矢量。 在这一阶段进行运动估计时，从至少一个分区大小的输入运动向量可以被用作搜索至少一个其他分区大小的候选运动矢量。