PREDICTOR CANDIDATES FOR MOTION COMPENSATION

    公开(公告)号:US20240073439A1

    公开(公告)日:2024-02-29

    申请号:US18373645

    申请日:2023-09-27

    摘要: Different implementations are described, particularly implementations for determining a set of predictor candidates for affine merge coding mode from neighboring blocks for motion compensation of a picture block based on a motion model. The motion model, may be, e.g., an affine model in a merge mode or AMVP mode for a video content encoder or decoder. The motion model, may be, e.g., an affine model based on top-left/top-right control point motion vectors or an affine model based on top-left/botton-left control point motion vectors. Such affine model may be signaled by a flag. In an embodiment, predictor candidates are sorted in the set based on a criterion such as, e.g., a validity check or a vectors coherence cost. In an embodiment, a predictor candidate is selected from the set based on a motion model for each of the multiple predictor candidates, and may be based on a criterion such as, e.g., a rate distortion cost. The corresponding motion field is determined based on, e.g., one or more corresponding control point motion vectors for the block being encoded or decoded. The corresponding motion field of an embodiment identifies motion vectors used for prediction of sub-blocks of the block being encoded or decoded.

    Alternating frame processing operation with predicted frame comparisons for high safety level use

    公开(公告)号:US11895326B2

    公开(公告)日:2024-02-06

    申请号:US18079237

    申请日:2022-12-12

    摘要: Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs), with only frame checking microprocessors operating in a lockstep mode. In one example, two DSP are operating on alternate frames. Each DSP processes the frames and produces prediction values for the next frame. The lockstep microprocessors develop their own next frame prediction. The lockstep processors compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable. In another example, hardware checkers are provided to compare the present frame with a larger number of prior frames. The hardware checkers provide comparison results to the lockstep processors to compare against allowable variation limits.

    TECHNIQUES OF MULTI-HYPOTHESIS MOTION COMPENSATION

    公开(公告)号:US20190246114A1

    公开(公告)日:2019-08-08

    申请号:US16257904

    申请日:2019-01-25

    申请人: Apple Inc.

    摘要: The present disclosure describes techniques for coding and decoding video in which a plurality of coding hypotheses are developed for an input pixel block of frame content. Each coding hypothesis may include generation of prediction data for the input pixel block according to a respective prediction search. The input pixel block may be coded with reference to a prediction block formed from prediction data derived according to plurality of hypotheses. Data of the coded pixel block may be transmitted to a decoder along with data identifying a number of the hypotheses used during the coding to a channel. At a decoder, an inverse process may be performed, which may include generation of a counterpart prediction block from prediction data derived according to the hypothesis identified with the coded pixel block data, then decoding of the coded pixel block according to the prediction data.

    VIDEO ENCODING APPARATUS AND VIDEO DATA AMOUNT ENCODING METHOD

    公开(公告)号:US20180199031A1

    公开(公告)日:2018-07-12

    申请号:US15794253

    申请日:2017-10-26

    发明人: He-Yuan LIN

    摘要: A video encoding apparatus is provided. A controller in the video encoding apparatus includes a sum calculating circuit, a data amount estimating circuit, and an evaluating circuit. Each of a plurality of intra-prediction and motion compensation modes corresponds to a set of transformed/quantized residual data. The sum calculating circuit calculates, for each set of transformed/quantized residual data, a sum of absolute values of non-zero elements therein and a sum of coordinate values of these non-zero elements relative to a reference point. The data amount estimating circuit generates, for each intra-prediction and motion compensation mode, an estimated data amount according to the sum of absolute values and the sum of absolute values of the coordinate values of corresponding transformed and quantized residual data. The evaluating circuit selects a best mode from the plurality of intra-prediction and motion compensation modes according to the plurality of estimated data amounts.