Abstract:
Embodiments of the present disclosure relate to generating motion vectors. An image signal processor includes a statistics circuit and a vector correlation analysis circuit. The statistics circuit determines image statistics such as vectors representing sums of pixel values of rows or columns of blocks of an image. Additionally, the statistics circuit may mix or aggregate sums of multiple color components. The vector correlation analysis performs cross-correlation between vectors of a current image and reference vectors of a prior image to determine cross-correlation scores. The vector correlation analysis generates a motion vector by identifying shifts in horizontal and vertical directions corresponding to peak values of cross-correlation scores.
Abstract:
System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes bit-rate statistics generation that is useful for controlling subsequent bit rates and/or determining encoding operational modes.
Abstract:
A video encoder may include a context-adaptive binary arithmetic coding (CABAC) encode component that converts each syntax element of a representation of a block of pixels to binary code, serializes it, and codes it mathematically with its probability model, after which the resulting bit stream is output. When the probability of a bin being coded with one of two possible symbols is one-half, the bin may be coded using bypass bin coding mode rather than a more compute-intensive regular bin coding mode. The CABAC encoder may code multiple consecutive bypass bins in a series of cascaded processing units during a single processing cycle (e.g., a regular bin coding cycle). Intermediate outputs of each processing unit may be coupled to inputs of the next processing unit. A resolver unit may accept intermediate outputs of the processing units and generate final output bits for the bypass bins.
Abstract:
Embodiments of the present disclosure relate to generating motion vectors. An image signal processor includes a statistics circuit and a vector correlation analysis circuit. The statistics circuit determines image statistics such as vectors representing sums of pixel values of rows or columns of blocks of an image. Additionally, the statistics circuit may mix or aggregate sums of multiple color components. The vector correlation analysis performs cross-correlation between vectors of a current image and reference vectors of a prior image to determine cross-correlation scores. The vector correlation analysis generates a motion vector by identifying shifts in horizontal and vertical directions corresponding to peak values of cross-correlation scores.
Abstract:
System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes a transcode pipeline that provides entropy encoding of binarized syntax elements. More specifically, multiple bins may be encoded in parallel, resulting in increased encoding throughput.
Abstract:
Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.
Abstract:
Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.
Abstract:
System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes a transcode pipeline that provides entropy encoding of binarized syntax elements. More specifically, multiple bins may be encoded in parallel, resulting in increased encoding throughput.
Abstract:
System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes bit-rate statistics generation that is useful for controlling subsequent bit rates and/or determining encoding operational modes.
Abstract:
A video encoder may include a context-adaptive binary arithmetic coding (CABAC) encode component that converts each syntax element of a representation of a block of pixels to binary code, serializes it, and codes it mathematically with its probability model, after which the resulting bit stream is output. When the probability of a bin being coded with one of two possible symbols is one-half, the bin may be coded using bypass bin coding mode rather than a more compute-intensive regular bin coding mode. The CABAC encoder may code multiple consecutive bypass bins in a series of cascaded processing units during a single processing cycle (e.g., a regular bin coding cycle). Intermediate outputs of each processing unit may be coupled to inputs of the next processing unit. A resolver unit may accept intermediate outputs of the processing units and generate final output bits for the bypass bins.