公开(公告)号：US11664086B2

公开(公告)日：2023-05-30

申请号：US17375887

申请日：2021-07-14

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Bikas Maiti ,  Vivek Nautiyal

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/18

CPC classification number: G11C29/76 ,  G11C7/1012 ,  G11C29/18 ,  G11C29/785 ,  G11C2029/1802

Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

公开(公告)号：US11586445B2

公开(公告)日：2023-02-21

申请号：US16698862

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Shardendu Shekhar ,  Andy Wangkun Chen ,  Anil Kumar Baratam ,  James Dennis Dodrill ,  Yew Keong Chong

IPC: G06F9/38 ,  G06F7/53 ,  G06F7/544 ,  G06F9/30 ,  G06F12/02

Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.

公开(公告)号：US11532353B2

公开(公告)日：2022-12-20

申请号：US17162532

申请日：2021-01-29

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Rahul Mathur ,  Andy Wangkun Chen

IPC: G11C11/41 ,  G11C11/419 ,  G11C11/418

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

公开(公告)号：US11521703B2

公开(公告)日：2022-12-06

申请号：US17218927

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Amandeep Kaur ,  Andy Wangkun Chen ,  Penaka Phani Goberu ,  Khushal Gelda

IPC: G11C29/00 ,  G11C29/44 ,  G01R31/3193

Abstract: Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.

公开(公告)号：US11514979B2

公开(公告)日：2022-11-29

申请号：US17218949

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Munish Kumar ,  Ayush Kulshrestha ,  Rajiv Kumar Sisodia ,  Yew Keong Chong ,  Kumaraswamy Ramanathan ,  Edward Martin McCombs, Jr.

IPC: G11C8/00 ,  G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

公开(公告)号：US11468945B2

公开(公告)日：2022-10-11

申请号：US17071449

申请日：2020-10-15

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Joel Thornton Irby ,  Andy Wangkun Chen

IPC: G11C11/418 ,  G11C11/419

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

公开(公告)号：US20220319632A1

公开(公告)日：2022-10-06

申请号：US17218927

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Amandeep Kaur ,  Andy Wangkun Chen ,  Penaka Phani Goberu ,  Khushal Gelda

IPC: G11C29/00 ,  G01R31/3193 ,  G11C29/44

Abstract: Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.

公开(公告)号：US20220293522A1

公开(公告)日：2022-09-15

申请号：US17199143

申请日：2021-03-11

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Ettore Amirante ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sony .

IPC: H01L23/528 ,  G06F30/3953 ,  H01L23/522 ,  G06F119/06

Abstract: Various implementations described herein are directed to a method for routing buried power rails underneath a memory instance. The method may identify first rails of the buried power rails disposed in a first layer and second rails of the buried power rails disposed perpendicular to the first rails in a second layer. The method may identify long rails of the first rails with a first length and short rails of the first rails with a second length that is less than the first length. The method may separately couple the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer.

公开(公告)号：US11443777B2

公开(公告)日：2022-09-13

申请号：US17019030

申请日：2020-09-11

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C7/04 ,  G11C5/14 ,  G11C8/08

Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.

公开(公告)号：US11328750B1

公开(公告)日：2022-05-10

申请号：US17155400

申请日：2021-01-22

Applicant: Arm Limited

Inventor： Ettore Amirante ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sony

IPC: G11C5/14 ,  H01L23/528 ,  H01L27/02 ,  G11C17/12

Abstract: Various implementations described herein are related to a device with a backside power network. The backside power network may have a buried power rail that is coupled to ground. The device may have a read-only memory (ROM) cell that is coupled between at least one bitline and the buried power rail, and the ROM cell may be coupled to ground by way of the buried power rail.