公开(公告)号：US08629515B2

公开(公告)日：2014-01-14

申请号：US13245494

申请日：2011-09-26

申请人： Ching-Han Yeh ,  Chen-Pin Hsu ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang

发明人： Ching-Han Yeh ,  Chen-Pin Hsu ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

摘要： A semiconductor device includes a semiconductor substrate, a source and a drain region formed on the semiconductor substrate, and a gate structure disposed on the substrate between the source and drain regions. The gate structure includes an interfacial layer formed over the substrate, a high-k dielectric formed over the interfacial layer, and a metal gate formed over the high-k dielectric that includes a first metal layer and a second metal layer, where the first metal layer is formed on a portion of the sidewalls of the gate structure and where the second metal layer is formed on another portion of the sidewalls of the gate structure.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的源极和漏极区域以及设置在源极和漏极区域之间的衬底上的栅极结构。 栅极结构包括在衬底上形成的界面层，在界面层上形成的高k电介质，以及形成在包括第一金属层和第二金属层的高k电介质上的金属栅，其中第一金属 层形成在栅极结构的侧壁的一部分上，并且第二金属层形成在栅极结构的侧壁的另一部分上。

公开(公告)号：US08487382B2

公开(公告)日：2013-07-16

申请号：US13292665

申请日：2011-11-09

申请人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/70

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

摘要翻译： 本公开提供了制造半导体器件的金属栅叠层的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

公开(公告)号：US08461654B2

公开(公告)日：2013-06-11

申请号：US13270585

申请日：2011-10-11

申请人： Ming-Yuan Wu ,  Yi-Shien Mor ,  Chih-Tang Peng ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

发明人： Ming-Yuan Wu ,  Yi-Shien Mor ,  Chih-Tang Peng ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.

摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

公开(公告)号：US08334572B2

公开(公告)日：2012-12-18

申请号：US13216034

申请日：2011-08-23

申请人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L23/62

CPC分类号： H01L23/5256 ,  H01L21/823878 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.

摘要翻译： 提供了一种半导体器件，其包括半导体衬底，形成在衬底中用于隔离衬底的有源区的隔离结构，隔离结构由第一材料形成，有源器件形成在衬底的有源区中， 具有高k电介质和金属栅极的有源器件和形成在隔离结构中的无源器件，无源器件由不同于第一材料并具有预定电阻率的第二材料形成。

公开(公告)号：US20120132987A1

公开(公告)日：2012-05-31

申请号：US13367103

申请日：2012-02-06

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823475 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/7846

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。 第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。 第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。 该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

公开(公告)号：US08173491B2

公开(公告)日：2012-05-08

申请号：US13074914

申请日：2011-03-29

申请人： Oscar M. K. Law ,  Manoj Achyutrao Joshi ,  Kong-Beng Thei ,  Harry Chuang

发明人： Oscar M. K. Law ,  Manoj Achyutrao Joshi ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L27/11807 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

摘要翻译： 公开了具有层与单元边界间隔的可变规则的标准单元布局的结构和方法。 在一个实施例中，第一标准单元布局设置有导电层，其具有间隔最小间隔距离的至少两个部分，所述导电层具有至少一个与单元边界隔开的部分，第一间隔距离小于一半 的最小间距; 与所述第一标准单元相邻设置的第二标准单元，所述第二单元中的所述导电层的至少一个第二部分与所述第一标准单元中的所述第一部分相邻设置，并且与所述第一标准单元间隔开第二间隔， 最小 其中所述第一和第二间距的总和至少与所述最小间隔一样大。 公开了一种形成标准的方法。

公开(公告)号：US08138554B2

公开(公告)日：2012-03-20

申请号：US12212034

申请日：2008-09-17

申请人： Harry Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76895 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/4238

摘要： A semiconductor device with local interconnects is provided. The semiconductor device comprises a first gate line structure and a second gate line structure disposed on a substrate and substantially collinear. A first pair of source/drain regions is formed in the substrate on both sides of the first gate line structure and a second pair of source/drain regions is formed in the substrate on both sides of the second gate line structure. A pair of conductive lines is disposed on the substrate on both sides of the first gate line structure and the second gate line structure, such that each conductive line is connected to one of the first pair of source/drain regions and one of the second pair of source/drain regions.

摘要翻译： 提供具有局部互连的半导体器件。 半导体器件包括设置在衬底上并基本上共线的第一栅极线结构和第二栅极线结构。 第一对源极/漏极区域形成在第一栅极线结构的两侧的衬底中，并且第二对源极/漏极区域形成在第二栅极线结构的两侧的衬底中。 一对导线设置在第一栅极线结构和第二栅极线结构的两侧上的衬底上，使得每个导线连接到第一对源极/漏极区域中的一个并且第二对中的一个 的源/漏区。

公开(公告)号：US20120056269A1

公开(公告)日：2012-03-08

申请号：US13292665

申请日：2011-11-09

申请人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

摘要翻译： 本公开提供了制造半导体器件的金属栅叠层的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

公开(公告)号：US08115271B2

公开(公告)日：2012-02-14

申请号：US13155251

申请日：2011-06-07

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

IPC分类号： H01L21/70

CPC分类号： H01L21/823475 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/7846

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。 第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。 第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。 该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

公开(公告)号：US08105891B2

公开(公告)日：2012-01-31

申请号：US12944221

申请日：2010-11-11

申请人： Chiung-Han Yeh ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chiung-Han Yeh ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within the first trench but not the second trench. A second metal layer and a third metal layer are formed in the first and second trenches. A thermal process is used to reflow the second metal layer and the third metal layer.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上形成第一沟槽和第二沟槽，并在第一和第二沟槽中形成第一金属层。 然后至少部分地从第一沟槽内除去第一金属层而不是第二沟槽。 在第一和第二沟槽中形成第二金属层和第三金属层。 使用热处理来回流第二金属层和第三金属层。