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243 条记录 (耗时 0.026 秒)

    Integrating a first contact structure in a gate last process
    2.
    发明授权
    Integrating a first contact structure in a gate last process 有权
    在最后一个进程中集成第一个接触结构

    公开(公告)号：US08035165B2

    公开(公告)日：2011-10-11

    申请号：US12341891

    申请日：2008-12-22

    申请人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

    摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

    摘要翻译： 提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。 所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。

    Method for semiconductor device performance enhancement
    3.
    发明授权
    Method for semiconductor device performance enhancement 有权
    半导体器件性能提高的方法

    公开(公告)号：US07632729B2

    公开(公告)日：2009-12-15

    申请号：US11527616

    申请日：2006-09-27

    申请人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

    发明人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

    摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

    摘要翻译： 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

    Reducing Device Performance Drift Caused by Large Spacings Between Action Regions
    4.
    发明申请
    Reducing Device Performance Drift Caused by Large Spacings Between Action Regions 有权
    减少行动区域之间大间距引起的设备性能漂移

    公开(公告)号：US20090273052A1

    公开(公告)日：2009-11-05

    申请号：US12175976

    申请日：2008-07-18

    申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

    发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

    IPC分类号： H01L21/322 ,  H01L27/10

    CPC分类号： H01L21/823475 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/7846

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

    摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。 第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。 第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。 该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

    Dishing-free gap-filling with multiple CMPs
    5.
    发明授权
    Dishing-free gap-filling with multiple CMPs 有权

    公开(公告)号：US08552522B2

    公开(公告)日：2013-10-08

    申请号：US13151666

    申请日：2011-06-02

    申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76883 ,  H01L21/76229

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

    Semiconductor device and method of fabricating same
    6.
    发明授权
    Semiconductor device and method of fabricating same 有权
    半导体装置及其制造方法

    公开(公告)号：US08461629B2

    公开(公告)日：2013-06-11

    申请号：US13178755

    申请日：2011-07-08

    申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

    摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

    摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

    Semiconductor device with both I/O and core components and method of fabricating same
    9.
    发明授权
    Semiconductor device with both I/O and core components and method of fabricating same 有权
    具有I / O和核心部件的半导体器件及其制造方法

    公开(公告)号：US07998830B2

    公开(公告)日：2011-08-16

    申请号：US12961167

    申请日：2010-12-06

    申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L21/76

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

    摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

    摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

    INTEGRATING A CAPACITOR IN A METAL GATE LAST PROCESS
    10.
    发明申请
    INTEGRATING A CAPACITOR IN A METAL GATE LAST PROCESS 有权
    在金属门最后过程中集成电容器

    公开(公告)号：US20100001332A1

    公开(公告)日：2010-01-07

    申请号：US12256132

    申请日：2008-10-22

    申请人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

    发明人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

    IPC分类号： H01L29/92 ,  H01L21/34

    CPC分类号： H01L27/0629 ,  H01L27/11 ,  H01L29/94

    摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.

    摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。 所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料 电极。