公开(公告)号：US20110148620A1

公开(公告)日：2011-06-23

申请号：US13039832

申请日：2011-03-03

Applicant: David C. McClure ,  Sooping Saw ,  Robert Wadsworth

Inventor： David C. McClure ,  Sooping Saw ,  Robert Wadsworth

IPC: G08B29/00

CPC classification number: G11C16/20 ,  G11C16/22 ,  G11C17/16

Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode. More specifically, the second circuit operates to drive the alarm output pad with the tamper alarm signal when the integrated circuit is not in test mode and drive the test mode output pad with the tamper alarm signal when the integrated circuit is in test mode (with the alarm output pad driven to a known state).

Abstract translation: 集成电路包括输出焊盘，报警输出焊盘和测试模式输出焊盘。 第一个多位寄存器是可编程的，用于存储可编程数据，例如识别已经制造了集成电路的客户的数据。 可编程第二个多位寄存器来存储客户指定的阈值数据。 第一电路将第一和第二多位寄存器选择性地耦合到输出焊盘。 第一电路可操作地响应于集成电路被放置在测试模式中，以执行存储在第一多位寄存器中的客户识别数据或存储在第二多位寄存器中的客户指定的阈值数据的并行 - 串行转换， 位寄存器，并通过输出板驱动转换后的数据输出。 集成电路还包括可响应于客户指定的阈值数据操作的篡改检测电路，以产生篡改报警信号。 第二电路根据集成电路是否处于测试模式，选择性地将篡改报警信号耦合到报警输出焊盘和测试模式输出焊盘。 更具体地，当集成电路不处于测试模式时，第二电路用于驱动具有篡改报警信号的报警输出板，并且当集成电路处于测试模式时驱动具有篡改报警信号的测试模式输出板 报警输出板驱动到已知状态）。

公开(公告)号：US20100165709A1

公开(公告)日：2010-07-01

申请号：US12645039

申请日：2009-12-22

Applicant: Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  Francois Jacquet

Inventor： Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  Francois Jacquet

IPC: G11C11/00 ,  G11C5/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/417

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract translation: 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约在高和低SRAM电源的电压之间的一半的电压。

公开(公告)号：US07688669B2

公开(公告)日：2010-03-30

申请号：US12029366

申请日：2008-02-11

Applicant: David C. McClure ,  Mark A. Lysinger ,  Mehdi Zamanian ,  François Jacquet ,  Philippe Roche

Inventor： David C. McClure ,  Mark A. Lysinger ,  Mehdi Zamanian ,  François Jacquet ,  Philippe Roche

IPC: G11C7/00

CPC classification number: G11C11/417 ,  G11C5/147 ,  G11C5/148 ,  G11C11/41 ,  G11C11/413 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract translation: 存储电路具有高电压和低电压电源节点。 根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。 如果处于主动读/写模式，则选择性地施加第一组电压。 相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。 所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压 所述第一组电压通过多个高偏移电压中的所选择的一个。 偏移电压由选择性有效的基于二极管的电路提供。 选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。

公开(公告)号：US07327544B2

公开(公告)日：2008-02-05

申请号：US10890964

申请日：2004-07-14

Applicant: David C. McClure ,  William D. Bishop

Inventor： David C. McClure ,  William D. Bishop

IPC: H02H3/20 ,  H02H9/08 ,  H02J7/00

CPC classification number: H02J7/0031

Abstract: A battery protection structure is described. The structure provides battery overcharging protection while allowing for minimal battery voltage drop during normal battery operation. One resistance element sets voltage drop during normal operation, and the sum of two resistance elements sets the maximum battery charging current which will be allowed. The structure provides protection against single component failures.

Abstract translation: 描述了电池保护结构。 该结构提供电池过充保护，同时允许在正常电池操作期间最小的电池电压降。 一个电阻元件在正常工作期间设定电压降，两个电阻元件之和设定允许的最大电池充电电流。 该结构提供了防止单组件故障的保护。

公开(公告)号：US07064534B2

公开(公告)日：2006-06-20

申请号：US10695294

申请日：2003-10-27

Applicant: David C. McClure ,  Mehdi Zamanian

Inventor： David C. McClure ,  Mehdi Zamanian

IPC: G05F3/16

CPC classification number: G05F3/247 ,  Y10T307/615 ,  Y10T307/696

Abstract: A regulator circuit and method are disclosed for a system. The regulator circuit may include a compare circuit for comparing a first supply voltage to a predetermined voltage level and generating an enable signal based upon the comparison. A selectively enabled voltage regulator is adapted to make available a predetermined current level at a regulated voltage when enabled by the compare circuit. When disabled, the voltage regulator circuit is prohibited from providing current. The voltage regulator may include an output transistor that is normally biased in a saturation mode of operation and is deactivated by the enable signal. By controlling the output transistor based upon the output of the compare circuit, the need for a relatively large transistor for connecting to the first supply voltage is eliminated.

Abstract translation: 公开了一种用于系统的调节器电路和方法。 调节器电路可以包括用于将第一电源电压与预定电压电平进行比较并基于该比较产生使能信号的比较电路。 当由比较电路使能时，有选择地使能的电压调节器适于使得在调节电压下可用的预定电流电平。 禁用时，电压调节器电路禁止提供电流。 电压调节器可以包括通常在饱和运行模式下被偏置并由使能信号禁用的输出晶体管。 通过基于比较电路的输出控制输出晶体管，消除了用于连接到第一电源电压的相对大的晶体管的需要。

公开(公告)号：US07012417B2

公开(公告)日：2006-03-14

申请号：US10690332

申请日：2003-10-21

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G05B24/02 ,  H02J1/00

CPC classification number: G05F3/242

Abstract: An electronic device incorporates a primary function circuit and a voltage regulator that provides a regulated voltage signal to the primary function circuit. The voltage regulator is responsive to a stress-enable signal indicative of whether or not an external voltage supplied to the voltage detector is within a predetermined range. The output voltage signal is controlled to be at a first voltage level when the external voltage is within the predetermined voltage range and at a second voltage level when the external voltage is outside of the predetermined range. The second voltage level may be an elevated voltage level to facilitate stress testing or burin-in of the electronic device.

Abstract translation: 电子设备包括主功能电路和向主功能电路提供调节电压信号的电压调节器。 电压调节器响应于指示供应到电压检测器的外部电压是否在预定范围内的应力使能信号。 当外部电压在预定电压范围内时，输出电压信号被控制在第一电压电平，并且当外部电压在预定范围之外时被控制在第二电压电平。 第二电压电平可以是升高的电压电平，以便于电子装置的压力测试或加压。

公开(公告)号：US06990011B2

公开(公告)日：2006-01-24

申请号：US10695239

申请日：2003-10-27

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/00

CPC classification number: G11C11/4125

Abstract: A method and circuit are disclosed for an integrated circuit having one or more memory cells, each memory cell including first and second p-channel transistor and first and second n-channel transistors configured as cross-coupled logic inverters between first and second reference voltage levels during a normal mode of operation. Power control circuitry is coupled to a source terminal of the first p-channel transistor of each memory cell for providing to the first p-channel transistors the first reference voltage level during the normal mode of operation. This causes a first voltage less than the first reference voltage level to appear at the source terminal of the first p-channel transistors during a data corruption mode of operation wherein data stored in the one or more memory cells is corrupted.

Abstract translation: 公开了一种用于具有一个或多个存储单元的集成电路的方法和电路，每个存储单元包括第一和第二p沟道晶体管，以及第一和第二n沟道晶体管，被配置为第一和第二参考电压电平之间的交叉耦合逻辑反相器 在正常操作模式下。 功率控制电路耦合到每个存储单元的第一p沟道晶体管的源极端子，以在正常操作模式期间向第一p沟道晶体管提供第一参考电压电平。 这导致在数据损坏操作模式期间，小于第一参考电压电平的第一电压出现在第一p沟道晶体管的源极端，其中存储在一个或多个存储器单元中的数据被破坏。

公开(公告)号：US06750683B2

公开(公告)日：2004-06-15

申请号：US09846524

申请日：2001-04-30

Applicant: David C. McClure ,  Rong Yin

Inventor： David C. McClure ,  Rong Yin

IPC: H03K522

CPC classification number: G01R19/16547

Abstract: A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first reference voltage signal. A comparator compares the unregulated power supply voltage to the trimmed reference voltage signal and asserts an output signal based upon the comparison. The output signal is fed back as an input to the trim circuit so that the trim circuit provides a hysteresis effect.

Abstract translation: 公开了一种用于监测未调节电源的电压电平的电路和方法。 电路包括用于产生第一参考电压信号的电压参考电路和基于第一参考电压信号产生修整的参考电压信号的微调电路。 比较器将未调节的电源电压与修整的参考电压信号进行比较，并根据比较确定输出信号。 输出信号作为输入反馈到微调电路，使得微调电路提供滞后效应。

公开(公告)号：US06476669B2

公开(公告)日：2002-11-05

申请号：US09902206

申请日：2001-07-10

Applicant: David C. McClure ,  Rong Yin

Inventor： David C. McClure ,  Rong Yin

IPC: H03K1772

CPC classification number: G05F3/242

Abstract: A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistor's gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage. Pass gates control which end of the resistive load series is connected to the output of the voltage follower and which is connected to the output of the trim circuit. To decrement the reference voltage, a first end is connected to the output of the voltage follower and the second end is connected to trim circuit output; to increment the reference voltage, the second end of the resistive load series is connected to the voltage follower output and the first end is connected to the trim circuit output.

Abstract translation: 参考电压调整电路包括接收要修整的参考电压的电压跟随器，其中一个或多个电阻负载提供串联连接在电压跟随器的输出端和微调电路的输出之间的预定电压偏移。 电压跟随器包括电流反射镜差分放大器，其在一个输入处接收参考电压，并在另一个输入端接收电压跟随器的输出;以及晶体管，其电阻负载连接在电源电压之间并接收电流镜差分的输出 放大器在晶体管的门。 电阻负载提供变化的预选电压降，并且每个分压由对应的保险丝分流，整个电阻负载系列由主保险丝分流。 为了修整参考电压，至少主保险丝与熔断器一起分流电阻性负载，结合起来产生所需的调整电压。 通路控制电阻负载系列的哪一端连接到电压跟随器的输出端并连接到微调电路的输出。 为了减小参考电压，第一端连接到电压跟随器的输出端，第二端连接到微调电路输出; 为了增加参考电压，电阻负载系列的第二端连接到电压跟随器输出，第一端连接到微调电路输出。

公开(公告)号：US6037799A

公开(公告)日：2000-03-14

申请号：US758587

申请日：1996-11-27

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  H03K19/173

CPC classification number: G11C29/24 ,  G11C29/785 ,  G11C29/80 ,  G11C29/808 ,  G11C29/84

Abstract: A multiplexing circuit includes a reference terminal, a plurality of multiplexing input terminals, and a buffer having an input terminal and an output terminal. The multiplexing circuit also includes a plurality of first elements that each have a programmable conductivity and that are each serially coupled between a corresponding one of the multiplexing input terminals and the input terminal of the buffer. When one of the input signals is to be coupled to the multiplexer output terminal, the element corresponding to the selected input signal is programmed in a conductive state, and the remaining elements are programmed in a nonconductive state. When none of the input signals are selected, each element is programmed in a conductive state and the input signals each have the same value so as to prevent signal conflicts and short circuits at nodes within the multiplexing circuit.

Abstract translation: 复用电路包括参考终端，多个复用输入端和具有输入端和输出端的缓冲器。 多路复用电路还包括多个第一元件，每个第一元件具有可编程导电性并且各自串联耦合在相应的多路复用输入端子和缓冲器的输入端之间。 当输入信号中的一个要被耦合到多路复用器输出端时，对应于所选择的输入信号的元件被编程为导通状态，并且其余元件被编程为非导通状态。 当没有选择输入信号时，每个元件被编程为导通状态，并且输入信号各自具有相同的值，以便防止复用电路内的节点处的信号冲突和短路。