公开(公告)号：US20080071931A1

公开(公告)日：2008-03-20

申请号：US11929756

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/38

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20080046635A1

公开(公告)日：2008-02-21

申请号：US11849344

申请日：2007-09-03

申请人： Ming-Shiang Shen

发明人： Ming-Shiang Shen

IPC分类号： G06F13/00

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data storage medium is adapted to be accessed by a data terminal, and includes a processing unit connected to a memory device that stores a data file and security reference data possessed by a person authorized to access the data file, and an input-output interface circuit activable so as to establish communication with the data terminal. The processing unit is operable selectively in a programming mode and a data retrieving mode. The electronic data storage medium also includes a function key set for manually switching the electronic data storage medium between the programming mode and the data retrieving mode.

公开(公告)号：US07333364B2

公开(公告)日：2008-02-19

申请号：US11737336

申请日：2007-04-19

申请人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G11C16/06

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634 ,  G11C2211/5641

摘要： A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

摘要翻译： 闪存具有多级单元（MLC），每个单元可以存储多个位。 当发生错误时，单元块可以降级到较少的位/单元，或用于存储关键数据（如引导代码）。 来自单个MLC的位在多个页面之间进行分区，以使用错误校正码（ECC）来提高错误的可校正性。 响应于校准寄存器，由参考电压发生器产生较高的参考电压，校准寄存器可编程为改变上参考电压。 从较高参考电压产生一系列减小的参考值，并将其与位线电压进行比较。 比较结果由翻译逻辑翻译，生成读取数据和编程过程中和编程不足的信号。 降级的单元格使用相同的真值表，但生成较少的读取数据位。 通过使用相同的子状态来读取降级和全密度MLC单元，噪声余量被不对称地改善。

公开(公告)号：US20080005581A1

公开(公告)日：2008-01-03

申请号：US11900937

申请日：2007-09-13

申请人： Ming-Shiang Shen

发明人： Ming-Shiang Shen

IPC分类号： H04K1/00

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data storage medium is adapted to be accessed by a data terminal, and includes a processing unit connected to a memory device that stores a data file and security reference data possessed by a person authorized to access the data file, and an input-output interface circuit activable so as to establish communication with the data terminal. The processing unit is operable selectively in a programming mode and a data retrieving mode. The electronic data storage medium also includes a function key set for manually switching the electronic data storage medium between the programming mode and the data retrieving mode.

公开(公告)号：US20070283428A1

公开(公告)日：2007-12-06

申请号：US11471000

申请日：2006-09-07

申请人： Abraham C. Ma ,  Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

发明人： Abraham C. Ma ,  Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

IPC分类号： H04L9/32

CPC分类号： G06F11/1068 ,  G06F11/1076 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087 ,  H03M13/153 ,  H03M13/1535 ,  H03M13/1545 ,  H03M13/6561

摘要： An electronic data flash card accessible by a host computer, includes a flash memory controller connected to a flash memory device, and an input-output interface circuit activated to establish a communication with the host. In an embodiment, the flash card uses a USB interface circuit for communication with the host. A flash memory controller includes an arbitrator for mapping logical addresses with physical block addresses, and for performing block management operations including: storing reassigned data to available blocks, relocating valid data in obsolete blocks to said available blocks and reassigning logical block addresses to physical block addresses of said available blocks, finding bad blocks of the flash memory device and replacing with reserve blocks, erasing obsolete blocks for recycling after relocating valid data to available blocks, and erase count wear leveling of blocks, etc. Furthermore, each flash memory device includes an internal buffer for accelerating the block management operations.

摘要翻译： 由主机可访问的电子数据闪存卡包括连接到闪速存储器件的闪存控制器和被激活以建立与主机的通信的输入 - 输出接口电路。 在一个实施例中，闪存卡使用USB接口电路与主机进行通信。 闪速存储器控制器包括用于将逻辑地址与物理块地址对准的仲裁器，并且用于执行块管理操作，包括：将重新分配的数据存储到可用块，将过时块中的有效数据重定位到所述可用块并将逻辑块地址重新分配给物理块地址 的所述可用块，找到闪存设备的坏块并用备用块替换，在将有效数据重新定位到可用块之后擦除用于再循环的废弃块，以及擦除块的计数损耗均衡等。此外，每个闪存设备包括 内部缓冲区，用于加快块管理操作。

公开(公告)号：US07257714B1

公开(公告)日：2007-08-14

申请号：US09478720

申请日：2000-01-06

申请人： Ming-Shiang Shen

发明人： Ming-Shiang Shen

IPC分类号： H04K1/00 ,  H04L9/00

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： In an electronic data storage medium accessed by a data terminal, a fingerprint sensor scans a fingerprint of a user of the electronic data storage medium and generals fingerprint scan data. A processing unit is operable operable selectively in a programming mode, where the processing unit activates an input/output interface circuit to store a data file and fingerprint reference data obtained by scanning a fingerprint of a person authorized to access the data file in a memory device, and a data retrieving mode, where the processing unit activates the input/output interface circuit to transmit the data file to the data terminal upon verifying that the user of the electronic data storage medium is authorized to access the data file stored in the memory device as a result of comparison between the fingerprint scan data from the fingerprint sensor and the fingerprint reference data.

摘要翻译： 在由数据终端访问的电子数据存储介质中，指纹传感器扫描电子数据存储介质的用户的指纹，并指定扫描数据。 处理单元可操作地以编程模式可操作地操作，其中处理单元激活输入/输出接口电路以存储数据文件和通过扫描被授权访问存储器件中的数据文件的人的指纹而获得的指纹参考数据 以及数据检索模式，其中处理单元激活输入/输出接口电路，以在验证电子数据存储介质的用户被授权访问存储在存储器件中的数据文件之后将数据文件发送到数据终端 作为来自指纹传感器的指纹扫描数据与指纹参考数据之间的比较的结果。

公开(公告)号：US08171204B2

公开(公告)日：2012-05-01

申请号：US12115128

申请日：2008-05-05

申请人： David Q. Chow ,  Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/00

CPC分类号： G06F12/1416 ,  G06F3/0664 ,  G06F12/0851 ,  G06F12/0866 ,  G06F12/0897 ,  G06F21/32 ,  G06F21/78 ,  G06F21/79 ,  G06F2212/2022 ,  Y02D10/13

摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

摘要翻译： 闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。 多级缓存可以减少访问延迟。 电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。 闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。 具有NVMD的闪存系统可能包括用于安全性的指纹读取器。

公开(公告)号：US07966462B2

公开(公告)日：2011-06-21

申请号：US11871627

申请日：2007-10-12

申请人： Charles C. Lee ,  Frank Yu ,  Ming-Shiang Shen ,  Abraham C. Ma ,  David Q. Chow

发明人： Charles C. Lee ,  Frank Yu ,  Ming-Shiang Shen ,  Abraham C. Ma ,  David Q. Chow

IPC分类号： G06F12/02

CPC分类号： G06F12/0607 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/0408 ,  G11C2211/5649

摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

摘要翻译： 使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 还执行后台回收和ECC写入。

公开(公告)号：US07877542B2

公开(公告)日：2011-01-25

申请号：US12054310

申请日：2008-03-24

申请人： David Q. Chow ,  I-Kang Yu ,  Siew Sin Hiew ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  I-Kang Yu ,  Siew Sin Hiew ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G11C13/0004

摘要： High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically.

摘要翻译： 公开了非易失性存储器件（NVMD）的高集成度。 根据本发明的一个方面，非易失性存储器件包括智能非易失性存储器（NVM）控制器和智能非易失性存储器模块。 NVM控制器包括一个中央处理单元（CPU），用于处理对NVM模块的数据传输操作，以确保源同步接口，交错数据操作和块抽象寻址。 智能NVM模块包括接口逻辑，块地址管理器和至少一个非易失性存储器阵列。 接口逻辑被配置为处理物理块管理。 块地址管理器被配置为确保将物理地址转换为智能NVM控制器的CPU可访问的转换地址。 变换后的地址可以是逻辑上或物理上的块，页，扇区或字节中的地址。

公开(公告)号：US07855099B2

公开(公告)日：2010-12-21

申请号：US12423657

申请日：2009-04-14

申请人： Jim Chin-Nan Ni ,  Abraham C. Ma ,  Paul Hsueh ,  Ming-Shiang Shen

发明人： Jim Chin-Nan Ni ,  Abraham C. Ma ,  Paul Hsueh ,  Ming-Shiang Shen

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/02 ,  H01L23/498

CPC分类号： G06K19/077 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G06K19/07732 ,  G07C9/00087 ,  Y02D10/13

摘要： A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline.

摘要翻译： 闪存设备具有印刷电路板组件（PCBA），PCB组件具有闪存芯片和控制器芯片。 控制器芯片包括通过安全数字（SD）接口到外部计算机的输入/输出接口电路，以及从闪存芯片读取数据块的处理单元。 PCBA被封装在上壳体和下壳体内，PCB上的SD接触垫通过上壳体中的接触开口配合。 在每个SD接触垫和中肋下的支撑端肋以与设备中心线倾斜的角度支撑PCB。 PCB在远端向上倾斜，以允许安装在PCB底部表面的芯片的厚度更大，并且在插入端向下倾斜以将SD接触垫定位在中心线附近。