公开(公告)号：US20130015497A1

公开(公告)日：2013-01-17

申请号：US13119074

申请日：2011-02-18

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L29/0847 ,  H01L21/76805 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/78

摘要： An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.

摘要翻译： 提供包括第一区域和第二区域的S / D区域。 第一区域在衬底中具有至少部分厚度。 第二区域形成在第一区域上并且由与第一区域不同的材料制成。 还提供了形成S / D区域的方法，该方法包括：在基板中的栅叠层结构的两侧形成沟槽; 形成第一半导体层，其中所述第一半导体层的至少一部分被填充到所述沟槽中; 以及在所述第一半导体层上形成第二半导体层，其中所述第二半导体层由与所述第一半导体层不同的材料制成。 还提供接触孔及其形成方法，其可以增加接触孔和接触区域之间的接触面积，并降低接触电阻。

公开(公告)号：US20130011981A1

公开(公告)日：2013-01-10

申请号：US13614476

申请日：2012-09-13

申请人： Huilong Zhu ,  Jing Wang

发明人： Huilong Zhu ,  Jing Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/66651 ,  H01L29/7833

摘要： A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, a metal oxide semiconductor field effect transistor (MOFET) is provided that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions.

摘要翻译： 提供了具有高器件性能和改善的短沟道效应的半导体结构。 特别地，提供了一种金属氧化物半导体场效应晶体管（MOFET），其包括在该结构的反转层内的低掺杂浓度; 反型层是形成在半导体衬底的一部分顶上的外延半导体层。 该结构还包括在反转层下面的第一导电类型的阱区，其中阱区具有中心部分和两个水平邻接的端部。 中心部分具有比两个水平邻接端部更高的第一导电类型掺杂剂的浓度。

公开(公告)号：US20130001691A1

公开(公告)日：2013-01-03

申请号：US13381075

申请日：2011-08-25

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772 ,  H01L21/283

CPC分类号： H01L29/41733 ,  H01L21/76816 ,  H01L21/76882 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, and forming a gate structure on the SOI substrate; etching an SOI layer and a BOX layer of the SOI substrates on both sides of the gate structure, so as to form trenches exposing the BOX layer and extending partially into the BOX layer; forming metal sidewall spacers on sidewalls of the trenches, wherein the metal sidewall spacers is in contact with the SOI layer under the gate structure; forming an insulating layer filling partially the trenches, and forming a dielectric layer to cover the gate structure and the insulating layer; etching the dielectric layer to form first contact through holes that expose at least partially the insulating layer, and etching the insulating layer from the first contact through holes to form second contact through holes that expose at least partially the metal sidewall spacer; filling the first contact through holes and the second contact through holes to form contact vias, which are in contact with the metal sidewall spacers. The method provided by the present invention is capable of improving performance of semiconductor devices and alleviating manufacturing difficulty at the mean time.

摘要翻译： 本发明提供一种制造半导体结构的方法，其包括：提供SOI衬底，并在SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层并部分延伸到BOX层的沟槽; 在所述沟槽的侧壁上形成金属侧壁间隔物，其中所述金属侧壁间隔物与所述栅极结构下的所述SOI层接触; 形成部分填充沟槽的绝缘层，形成覆盖栅结构和绝缘层的电介质层; 蚀刻所述介电层以形成至少部分地暴露所述绝缘层的第一接触通孔，以及从所述第一接触通孔蚀刻所述绝缘层以形成至少部分地暴露所述金属侧壁间隔物的第二接触通孔; 通过孔和第二接触通孔填充第一接触件以形成与金属侧壁间隔件接触的接触通孔。 本发明提供的方法能够提高半导体装置的性能，同时能够减轻制造难度。

公开(公告)号：US08343818B2

公开(公告)日：2013-01-01

申请号：US12687287

申请日：2010-01-14

申请人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

IPC分类号： H01L21/84

CPC分类号： H01L21/187 ,  H01L21/6835 ,  H01L21/84 ,  H01L27/12 ,  H01L29/1083 ,  H01L2221/6835 ,  H01L2221/68368

摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.

公开(公告)号：US20120319185A1

公开(公告)日：2012-12-20

申请号：US13063653

申请日：2010-06-25

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed on the gate insulator layer, a first gate and a second gate on each side of the middle gate, first sidewall spacers between the first gate and the middle gate and between the second gate and the middle gate, and second sidewall spacers outside the first gate and the second gate, wherein, a first contact hole region is provided on the middle gate, second contact hole regions are provided respectively on the first gate and the second gate, and the first contact hole region and the second contact hole regions are in staggered arrangement. The present invention proposes a new NAND structure and a method of manufacturing the same. With the NAND structure, about 30-50% area of the chip may be effectively reduced.

摘要翻译： 本发明提供了一种NAND门结构，包括：衬底; 形成在所述基板上的栅极绝缘层; 形成在所述基板中的源极/漏极区域; 形成在栅极绝缘体层上的中间栅极，在中间栅极的每一侧上的第一栅极和第二栅极，第一栅极和中间栅极之间以及第二栅极和中间栅极之间的第一侧壁间隔物，以及第二侧壁间隔物 在第一栅极和第二栅极之外，其中，第一接触孔区域设置在中间栅极上，第二接触孔区域分别设置在第一栅极和第二栅极上，第一接触孔区域和第二接触孔 地区交错排列。 本发明提出了一种新的NAND结构及其制造方法。 利用NAND结构，芯片面积的30-50％可以有效降低。

公开(公告)号：US20120292766A2

公开(公告)日：2012-11-22

申请号：US12990990

申请日：2010-09-19

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/522 ,  H01L21/32051 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.

摘要翻译： 本发明提供一种半导体结构及其制造方法。 该方法包括：提供包括半导体器件的半导体衬底; 在所述半导体衬底上沉积铜扩散阻挡层; 在铜扩散阻挡层上形成铜复合层; 根据铜互连的形状，将要形成铜互连的相应位置处的铜复合物分解成铜; 并且在下面蚀刻未分解的铜复合物和铜扩散阻挡层，以使半导体器件互连。 本发明适用于制造集成电路中的互连。

公开(公告)号：US20120286337A1

公开(公告)日：2012-11-15

申请号：US13377141

申请日：2011-08-10

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L27/1211 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66545

摘要： Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

摘要翻译： 本发明的实施例公开了一种制造Fin场效应晶体管的方法。 当形成翅片时，在翅片上形成跨鳍片的虚拟栅极，在虚拟栅极的侧壁上形成间隔物，并且在第一介电层上形成覆盖层，并在模拟栅极外部形成覆盖层， 然后，通过间隔物在伪栅极的两侧形成自对准和升高的源/漏区，其中栅极和源极/漏极区的上表面在同一平面内。 栅极和源极/漏极区域的上表面位于相同的平面中，使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开，从而提高对准精度，解决接触插塞的不准确的对准以及提高器件AC性能。

公开(公告)号：US08299540B2

公开(公告)日：2012-10-30

申请号：US12754250

申请日：2010-04-05

申请人： Huilong Zhu ,  Jing Wang

发明人： Huilong Zhu ,  Jing Wang

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L21/26586 ,  H01L29/66651 ,  H01L29/7833

摘要： A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The inventive structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. Such a well region may be referred to as a non-uniform super-steep retrograde well.

摘要翻译： 提供了具有高器件性能和改善的短沟道效应的半导体结构。 特别地，本发明提供一种金属氧化物半导体场效应晶体管（MOFET），其包括在该结构的反转层内的低掺杂剂浓度; 反型层是形成在半导体衬底的一部分顶上的外延半导体层。 本发明的结构还包括在反转层下面的第一导电类型的阱区，其中阱区具有中心部分和两个水平邻接的端部。 中心部分具有比两个水平邻接端部更高的第一导电类型掺杂剂的浓度。 这样的井区域可以被称为不均匀的超陡逆行井。

公开(公告)号：US20120264262A1

公开(公告)日：2012-10-18

申请号：US13381014

申请日：2011-04-18

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7833 ,  H01L29/7847 ,  H01L29/7848

摘要： The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.

摘要翻译： 本发明涉及一种形成半导体结构的方法，包括：提供包括形成在其上的虚拟栅极的半导体衬底，围绕伪栅极的间隔物，分别形成在虚拟栅极两侧的源区和漏区，以及 形成在半导体衬底中并在虚拟栅极之下的沟道区; 去除虚拟门以形成门开口; 在闸门开口处形成应力材料层; 对所述半导体基板进行退火，所述应力材料层在退火时具有拉伸应力特性; 去除闸门开口中的应力材料层; 并在门开口形成门。 通过上述步骤，可以将应力记忆技术应用于pMOSFET。

公开(公告)号：US20120235244A1

公开(公告)日：2012-09-20

申请号：US13380482

申请日：2011-04-18

申请人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L27/088 ,  H01L29/772 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7835

摘要： A method for manufacturing a semiconductor structure comprises: providing a substrate, forming an active region on the substrate, forming a gate stack or a dummy gate stack on the active region, forming a source extension region and a drain extension region at opposite sides of the gate stack or dummy gate stack, forming a spacer on sidewalls of the gate stack or dummy gate stack, and forming a source and a drain on portions of the active region exposed by the spacer and the gate stack or dummy gate stack; removing at least a part of a source-side portion of the spacer, such that the source-side portion of the spacer has a thickness less than that of a drain-side portion of the spacer; and forming a contact layer on portions of the active region exposed by the spacer and the gate stack or dummy gate stack. Correspondingly, the present invention further provides a semiconductor structure. The present invention is beneficial to the reduction of the contact resistance of the source extension region and meanwhile can also reduce the parasitic capacitance between the gate and the drain extension region.

摘要翻译： 一种用于制造半导体结构的方法，包括：提供衬底，在衬底上形成有源区，在有源区上形成栅叠层或虚栅极叠层，在源极延伸区和漏极延伸区的相对两侧形成 栅极堆叠或伪栅极堆叠，在栅极堆叠或伪栅极堆叠的侧壁上形成间隔物，以及在由间隔物和栅极堆叠或伪栅极堆叠暴露的有源区域的部分上形成源极和漏极; 去除所述间隔物的源极侧部分的至少一部分，使得所述间隔物的源极侧部分的厚度小于所述间隔物的漏极侧部分的厚度; 以及在由间隔件和栅极堆叠或虚拟栅极堆叠暴露的有源区域的部分上形成接触层。 相应地，本发明还提供一种半导体结构。 本发明有益于降低源延伸区域的接触电阻，同时还可以减小栅极和漏极延伸区域之间的寄生电容。