公开(公告)号：US20080247492A1

公开(公告)日：2008-10-09

申请号：US11597794

申请日：2005-02-01

申请人： Hirokazu Sugimoto ,  Toru Iwata

发明人： Hirokazu Sugimoto ,  Toru Iwata

IPC分类号： H04L27/06

CPC分类号： G11B20/10009 ,  G09G5/006 ,  G09G5/12 ,  G11B20/10222 ,  G11B20/10425 ,  G11B20/14 ,  G11B2020/10592 ,  G11B2220/2562 ,  H04N5/775 ,  H04N5/781

摘要： In a signal receiving circuit including a plurality of input channels, there are provided N input detection circuits 2a to 2n for receiving clock signals S1-c to SN-c included in N channels of signals S1 to SN. Each of the input detection circuits 2a to 2n detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. If one of the input detection circuits 2a to 2n detects the input of the signal of the corresponding channel, the selection circuit 3 selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit 4, the serial/parallel conversion circuit 5, etc., which are shared by N channels. Therefore, there is needed only one each of input processing circuits such as the serial/parallel conversion circuit, thus saving the stand-by current for these input processing circuits.

摘要翻译： 在包括多个输入通道的信号接收电路中，设置有N个输入检测电路2a至2n，用于接收N个信号S 1至SN中包含的时钟信号S 1 -c至SN-c。 每个输入检测电路2a至2n检测相应信道的输入信号的转换，并进一步确认在转换检测之后正在接收相应信道的信号，从而检测相应信道的信号的输入 渠道。 如果输入检测电路2a至2n中的一个检测到对应信道的信号的输入，则选择电路3选择并输出检测到输入的信道的信号中的时钟信号和数据信号。 所选择的输出信号通过由N个信道共享的相位同步电路4，串行/并行转换电路5等中的每一个依次进行输入处理。 因此，仅需要一个输入处理电路，例如串行/并行转换电路，从而节省了用于这些输入处理电路的备用电流。

公开(公告)号：US07397268B2

公开(公告)日：2008-07-08

申请号：US11653340

申请日：2007-01-16

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

公开(公告)号：US20070115025A1

公开(公告)日：2007-05-24

申请号：US11653340

申请日：2007-01-16

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

公开(公告)号：US20070041483A1

公开(公告)日：2007-02-22

申请号：US11586587

申请日：2006-10-26

申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

IPC分类号： H03D3/24

CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

摘要翻译： 驱动器和接收器提供数据信号，其基于具有常规位模式的串行数据，例如时钟，其包括在调整周期期间彼此交替的1和0，并且基于具有任意的串行数据 在调整周期后的转移期间的位模式。 占空因数控制器调节驱动器或接收器的数据转换特性，使得从接收器提供的数据信号的占空比在调整周期中等于50％，并且具有被调整的数据转换特性。 时钟恢复单元恢复与在传送时段中从接收器提供的数据信号同步的时钟，并且基于来自数据信号的经调整的转换特性。

公开(公告)号：US07136441B2

公开(公告)日：2006-11-14

申请号：US10038613

申请日：2002-01-08

申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

IPC分类号： H04L7/00

CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

公开(公告)号：US20060194137A1

公开(公告)日：2006-08-31

申请号：US11363262

申请日：2006-02-28

申请人： Hiromichi Kobayashi ,  Toru Iwata ,  Toshio Honjo

发明人： Hiromichi Kobayashi ,  Toru Iwata ,  Toshio Honjo

IPC分类号： G03G9/10

CPC分类号： G03G9/107 ,  G03G9/1132

摘要： It is contemplated to provide irregular shaped ferrite carrier which has a lower resistance, a high specific surface area, a low specific gravity and a longer operational life, and an electrophotographic developer comprising the ferrite carrier which prevents the toner scattering, has a high image density, and is responsive to high-speed and color imaging. The irregular shaped ferrite carrier is characterized in that the carrier particles are irregular shaped, and 40 percent by number or more of the particles have a rock candy sugar shape and/or an oyster shell shape, and that the shape factor (SF-1=R2/S×π/4×100, wherein R is a maximum length and S is a projected area.) is 140 to 250, and the distribution width (δ) is 60 or less.

摘要翻译： 考虑到提供具有较低电阻，高比表面积，低比重和较长使用寿命的不规则形状的铁氧体载体，以及包含防止调色剂飞散的铁氧体载体的电子照相显影剂具有高图像密度 ，并且响应于高速和彩色成像。 不规则形状的铁氧体载体的特征在于，载体颗粒是不规则形状，并且40个数量以上的颗粒具有岩糖糖糖形状和/或牡蛎壳形状，并且形状因子（SF-1 = 其中，R为最大长度，S为投影面积）为140〜250，分布宽度（delta）为60以下。

公开(公告)号：US20060097772A1

公开(公告)日：2006-05-11

申请号：US11188855

申请日：2005-07-26

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

摘要翻译： 电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。 另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。

公开(公告)号：US20050231493A1

公开(公告)日：2005-10-20

申请号：US11071190

申请日：2005-03-04

申请人： Satoshi Takahashi ,  Ryogo Yanagisawa ,  Toru Iwata

发明人： Satoshi Takahashi ,  Ryogo Yanagisawa ,  Toru Iwata

IPC分类号： G09G5/00 ,  G06F13/14 ,  G09G3/20 ,  H03K5/19 ,  H03L7/00 ,  H04N5/14

CPC分类号： G09G5/006 ,  G09G3/2092

摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

摘要翻译： 用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。 当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。

公开(公告)号：US06633607B1

公开(公告)日：2003-10-14

申请号：US09249695

申请日：1999-02-12

申请人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

发明人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

IPC分类号： H03K904

CPC分类号： H03M9/00 ,  H04L25/49

摘要： A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.

摘要翻译： 一种半导体器件包括：发送部分; 以及接收部分，其中所述发送部分和所述接收部分通过总线相互连接，所述发送部分包括用于对包括多个比特的数据进行编码的编码部分，以产生指示至少的位置的比特位置信息 从包含在数据中的多个比特中选择一个比特，以及用于将比特位置信息输出到总线上的输出部分，并且接收部分包括用于从总线接收比特位置信息的输入部分和解码 用于解码位位置信息以产生数据。

公开(公告)号：US06542038B2

公开(公告)日：2003-04-01

申请号：US09986288

申请日：2001-11-08

申请人： Kazuko Nishimura ,  Toru Iwata

发明人： Kazuko Nishimura ,  Toru Iwata

IPC分类号： H03L700

CPC分类号： H03L7/087 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

摘要： A phase-offset detecting phase comparator for comparing a reference signal and an auxiliary comparison signal which is a frequency-divided VCO output in terms of a phase to detect phase offset, and producing first and second delay control signals corresponding to the phase offset; a first delay element for adding delay to the auxiliary comparison signal by the first delay control signal to produce a comparison signal; a second delay element for adding delay to the VCO output by the second delay control signal to produce a PLL output; and a dummy frequency divider for adding delay corresponding to a frequency divider to the PLL output are provided.

摘要翻译： 相位偏移检测相位比较器，用于比较基准信号和辅助比较信号，所述辅助比较信号是相位相位的分频VCO输出以检测相位偏移，并产生对应于相位偏移的第一和第二延迟控制信号; 第一延迟元件，用于通过第一延迟控制信号将延迟添加到辅助比较信号，以产生比较信号; 第二延迟元件，用于通过第二延迟控制信号向VCO输出添加延迟以产生PLL输出; 并且提供用于将对应于分频器的延迟添加到PLL输出的虚拟分频器。