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    QUASI-MONOLITHIC HIERARCHICAL INTEGRATION ARCHITECTURE
    112.
    发明申请
    QUASI-MONOLITHIC HIERARCHICAL INTEGRATION ARCHITECTURE 有权

    公开(公告)号：US20220406751A1

    公开(公告)日：2022-12-22

    申请号：US17354773

    申请日：2021-06-22

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Julien Sebot

    IPC: H01L25/065 ,  H01L23/00 ,  H01L21/683

    Abstract: A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.

    Piezoelectric devices fabricated in packaging build-up layers
    113.
    发明授权
    Piezoelectric devices fabricated in packaging build-up layers 有权

    公开(公告)号：US11508898B2

    公开(公告)日：2022-11-22

    申请号：US16397356

    申请日：2019-04-29

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Shawna M. Liff

    IPC: H01L41/053 ,  H01L41/23 ,  H01L41/047 ,  H01L41/332 ,  H03H9/10 ,  H01L41/09

    Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.

    Microelectronic assemblies with communication networks
    115.
    发明授权
    Microelectronic assemblies with communication networks 有权

    公开(公告)号：US11437348B2

    公开(公告)日：2022-09-06

    申请号：US17128558

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Amr Elshazly ,  Arun Chandrasekhar ,  Shawna M. Liff ,  Johanna M. Swan

    IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

    MICROELECTRONIC ASSEMBLIES
    116.
    发明申请
    MICROELECTRONIC ASSEMBLIES 有权

    公开(公告)号：US20220223578A1

    公开(公告)日：2022-07-14

    申请号：US17712339

    申请日：2022-04-04

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Arun Chandrasekhar

    IPC: H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

    INTER-COMPONENT MATERIAL IN MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING
    117.
    发明申请
    INTER-COMPONENT MATERIAL IN MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING 有权

    公开(公告)号：US20220189839A1

    公开(公告)日：2022-06-16

    申请号：US17122167

    申请日：2020-12-15

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Aleksandar Aleksov

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components. In some embodiments, the liner material, the inorganic fill material, and a material of the third microelectronic component may include a thermally conductive material.

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