公开(公告)号：US20230317660A1

公开(公告)日：2023-10-05

申请号：US17710518

申请日：2022-03-31

申请人： Intel Corporation

发明人： Zhaozhi Li ,  Feras Eid ,  Michael Baker ,  Wenhao Li ,  Pilin Liu ,  Johanna Swan

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L24/06 ,  H01L24/81 ,  H01L24/16 ,  H01L2224/1403 ,  H01L2224/10145 ,  H01L2224/0401 ,  H01L2224/81203 ,  H01L2224/16227 ,  H01L2224/14177

摘要： Microelectronic die package structures formed according to some embodiments may include a substrate having one or more solder structures. A first set of solder structures is located in a peripheral region of the substrate and a second set of solder structures is located in a central region of the substrate. A height of individual ones of the second set of solder structures is greater than a height of individual ones of the first set of solder structures. A die having a first side and a second side includes one or more conductive die pads on the first side, where individual ones of the conductive die pads are on individual ones of the first set solder structures and on individual ones of the second set solder structures. A die backside layer is on the second side of the die.

公开(公告)号：US20210366862A1

公开(公告)日：2021-11-25

申请号：US17392598

申请日：2021-08-03

申请人： Intel Corporation

发明人： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC分类号： H01L23/00

摘要： An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US11552035B2

公开(公告)日：2023-01-10

申请号：US17392598

申请日：2021-08-03

申请人： Intel Corporation

发明人： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC分类号： H01L23/00 ,  H01L23/498

摘要： An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US11127706B2

公开(公告)日：2021-09-21

申请号：US16145999

申请日：2018-09-28

申请人： Intel Corporation

发明人： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC分类号： H01L23/00

摘要： An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US20230317545A1

公开(公告)日：2023-10-05

申请号：US17710507

申请日：2022-03-31

申请人： Intel Corporation

发明人： Pilin Liu ,  Feras Eid ,  Michael Baker ,  Wenhao Li ,  Zhaozhi Li

IPC分类号： H01L23/367 ,  H01L23/00 ,  H01L23/373

CPC分类号： H01L23/367 ,  H01L24/16 ,  H01L24/17 ,  H01L24/08 ,  H01L24/09 ,  H01L24/81 ,  H01L23/3732 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2224/81203 ,  H01L2224/10155 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16237 ,  H01L2224/16014 ,  H01L2224/16013 ,  H01L2224/16057 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17132 ,  H01L2224/17133 ,  H01L2224/0801 ,  H01L2224/0903 ,  H01L2224/09104 ,  H01L2224/08113

摘要： Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

公开(公告)号：US10121722B1

公开(公告)日：2018-11-06

申请号：US15721880

申请日：2017-09-30

申请人： Intel Corporation

发明人： Chandra M. Jha ,  Eric J. Li ,  Zhaozhi Li ,  Robert M. Nickerson

IPC分类号： H01L23/34 ,  H01L23/373 ,  H01L23/00

摘要： A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.

公开(公告)号：US20230317676A1

公开(公告)日：2023-10-05

申请号：US17711926

申请日：2022-04-01

申请人： Intel Corporation

发明人： Michael Baker ,  Feras Eid ,  Wenhao Li ,  Zhaozhi Li ,  Pilin Liu

IPC分类号： H01L23/00 ,  B23K20/02

CPC分类号： H01L24/75 ,  H01L24/81 ,  B23K20/023 ,  H01L2224/05647 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/75983 ,  H01L2224/75984 ,  H01L2224/75985 ,  H01L2224/75312 ,  H01L2224/75252 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/75253 ,  B23K2101/40

摘要： Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) assembly including a bond head with a first thermal zone separated from a second thermal zone by a thermal separator, the thermal separator extending through a thickness of the bond head. A bond head nozzle is coupled to a first side of the bond head, where the bond head nozzle includes one or more nozzle channels extending through a thickness of the bond head nozzle.

公开(公告)号：US20230317675A1

公开(公告)日：2023-10-05

申请号：US17711925

申请日：2022-04-01

申请人： Intel Corporation

发明人： Michael Baker ,  Zhaozhi Li ,  Feras Eid ,  Pilin Liu ,  Wenhao Li

IPC分类号： H01L23/00

CPC分类号： H01L24/75 ,  H01L24/81 ,  H01L2224/81203 ,  H01L2224/75983 ,  H01L2224/75252

摘要： Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) tool including a pedestal having a convex surface to receive a package substrate, a bond head to compress a die against the package substrate, and a heat source thermally coupled to at least one of the pedestal or the bond head.

公开(公告)号：US20230317630A1

公开(公告)日：2023-10-05

申请号：US17710502

申请日：2022-03-31

申请人： Intel Corporation

发明人： Wenhao Li ,  Feras Eid ,  Michael Baker ,  Pilin Liu ,  Zhaozhi Li

IPC分类号： H01L23/00

CPC分类号： H01L23/562 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/81203

摘要： Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.

公开(公告)号：US11462527B2

公开(公告)日：2022-10-04

申请号：US16049696

申请日：2018-07-30

申请人： Intel Corporation

发明人： Kumar Abhishek Singh ,  Zhaozhi Li ,  Thomas J. Debonis ,  Robert Nickerson ,  Rees Winters

IPC分类号： H01L23/48 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/544 ,  H01L25/00

摘要： Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.