公开(公告)号：US20200051608A1

公开(公告)日：2020-02-13

申请号：US16523653

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Tae H. Kim ,  Charles L. Ingalls

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.

公开(公告)号：US10431282B2

公开(公告)日：2019-10-01

申请号：US16035135

申请日：2018-07-13

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US20190279984A1

公开(公告)日：2019-09-12

申请号：US16418150

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/108 ,  G11C11/4097 ,  H01L49/02 ,  G11C11/4094 ,  G11C5/02 ,  H01L29/08 ,  G11C11/408 ,  G11C11/403

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US10372566B2

公开(公告)日：2019-08-06

申请号：US15267817

申请日：2016-09-16

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner ,  Charles L. Ingalls

IPC: G06F11/00 ,  G06F11/20 ,  G11C11/22 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

公开(公告)号：US10347635B2

公开(公告)日：2019-07-09

申请号：US15986628

申请日：2018-05-22

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/108 ,  G11C11/408 ,  H01L49/02 ,  G11C11/4097 ,  H01L29/08 ,  G11C11/4094 ,  G11C5/02 ,  G11C11/403 ,  G11C11/4091

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US20180261302A1

公开(公告)日：2018-09-13

申请号：US15913413

申请日：2018-03-06

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Charles L. Ingalls

IPC: G11C29/50 ,  G11C29/00 ,  G11C11/22

CPC classification number: G11C29/50 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/70 ,  G11C2029/5006

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric current relationship, such as a short, between cells that make up the pair. Cells may be arranged in cell plate groups, and a pair of cells may include a first cell plate from one cell plate group and a second cell plate from the same cell plate group or from another, adjacent cell plate group. So a pair of cell plates may include cell plates from different cell plate groups. The first and second cell plates may be selected as a pair or a group based at least in part on the electric current relationship between the cell plates.

公开(公告)号：US20180158502A1

公开(公告)日：2018-06-07

申请号：US15844145

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.

公开(公告)号：US20180102158A1

公开(公告)日：2018-04-12

申请号：US15831076

申请日：2017-12-04

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric latch may be positioned anywhere in the memory device. In some instances, a ferroelectric latch may be positioned and configured to be dedicated to single piece of circuitry in the memory device.

公开(公告)号：US09847117B1

公开(公告)日：2017-12-19

申请号：US15276139

申请日：2016-09-26

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.

公开(公告)号：US09715919B1

公开(公告)日：2017-07-25

申请号：US15188890

申请日：2016-06-21

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.