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公开(公告)号：US10896932B2
公开(公告)日：2021-01-19
申请号：US16513797
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli
Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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公开(公告)号：US10748615B2
公开(公告)日：2020-08-18
申请号：US16419831
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Hongmei Wang , Luca Crespi , Debayan Mahalanabis , Fabio Pellizzer
IPC: G11C13/00
Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.
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公开(公告)号：US10734446B2
公开(公告)日：2020-08-04
申请号：US15854656
申请日：2017-12-26
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer
Abstract: A three dimensional (3D) memory array is disclosed. The 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in a same plane as the electrode plane, and the memory cell is configured to exhibit a first threshold voltage representative of a first logic state and a second threshold voltage representative of a second logic state. A conductive pillar is disposed through and coupled to the memory cell, wherein the conductive pillar and electrode plane are configured to provide a voltage across the memory cell to write a logic state to the memory cell. Methods to operate and to form the 3D memory array are disclosed.
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公开(公告)号：US10593399B2
公开(公告)日：2020-03-17
申请号：US15925536
申请日：2018-03-19
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer , Agostino Pirovano , Russell L. Meyer
IPC: G11C13/00 , H01L23/528
Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
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公开(公告)号：US10541364B2
公开(公告)日：2020-01-21
申请号：US15893108
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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Patent Agency Ranking
公开(公告)号：US10510957B2
公开(公告)日：2019-12-17
申请号：US15660829
申请日：2017-07-26
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Andrea Redaelli , Innocenzo Tortorelli
Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
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公开(公告)号：US20190341425A1
公开(公告)日：2019-11-07
申请号：US16513797
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli
Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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公开(公告)号：US10460798B2
公开(公告)日：2019-10-29
申请号：US16158353
申请日：2018-10-12
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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公开(公告)号：US20190311768A1
公开(公告)日：2019-10-10
申请号：US16419831
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Hongmei Wang , Luca Crespi , Debayan Mahalanabis , Fabio Pellizzer
IPC: G11C13/00
Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.
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公开(公告)号：US20190295642A1
公开(公告)日：2019-09-26
申请号：US16372010
申请日：2019-04-01
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Davide Fugazza , Johannes A. Kalb
IPC: G11C13/00
Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.
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