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    Methods, Devices and Systems for an Improved Management of a Non-Volatile Memory
    112.
    发明申请
    Methods, Devices and Systems for an Improved Management of a Non-Volatile Memory 有权

    公开(公告)号：US20220068367A1

    公开(公告)日：2022-03-03

    申请号：US17404487

    申请日：2021-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Dionisio Minopoli ,  Marco Sforzin ,  Daniele Balluchi

    IPC: G11C11/406 ,  G11C11/4076

    Abstract: A method including obtaining temperature values of at least one region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of such at least one region of the non-volatile memory, summing subsequent computed values of said operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the at least one region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on said comparison, performing a management operation on the cells of the at least one region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.

    SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM
    113.
    发明申请
    SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM 有权

    公开(公告)号：US20210406169A1

    公开(公告)日：2021-12-30

    申请号：US16962726

    申请日：2019-10-09

    Applicant: Micron Technology, Inc.

    Inventor： Dionisio Minopoli ,  Daniele Balluchi ,  Gianfranco Ferrante

    IPC: G06F12/02 ,  G06F12/06

    Abstract: A memory device is provided. The memory device comprises: a plurality of memory cells, each memory cell being programmable to at least two logic states, each logic state corresponding to a respective nominal electric resistance value of the memory cell, the plurality of memory cells comprising a first group of memory cells and a second group of memory cells, the memory cells of the second group being programmed to a predefined logic state of said at least two logic states; a memory controller coupled to the plurality of memory cells and configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation to assess the logic state thereof. The memory controller is further configured to: apply the reading voltage to the memory cells of the second group to assess the logic state thereof; if the logic state of at least one memory cell of the second group is assessed to be different from said predefined logic state, perform a refresh operation of the memory cells of the first group by applying thereto a recovery voltage higher than the reading voltage to assess the logic state thereof and then reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

    Apparatuses and methods for counter update operations
    114.
    发明授权
    Apparatuses and methods for counter update operations 有权

    公开(公告)号：US11055000B2

    公开(公告)日：2021-07-06

    申请号：US16905030

    申请日：2020-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Robert N. Hasbun ,  Daniele Balluchi

    IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

    Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

    COMMAND QUEUING
    115.
    发明申请
    COMMAND QUEUING 有权

    公开(公告)号：US20210200478A1

    公开(公告)日：2021-07-01

    申请号：US17140625

    申请日：2021-01-04

    Applicant: Micron Technology, Inc.

    Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

    IPC: G06F3/06

    Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

    Determination of data integrity based on sentinel cells
    116.
    发明授权
    Determination of data integrity based on sentinel cells 有权

    公开(公告)号：US10983727B2

    公开(公告)日：2021-04-20

    申请号：US16557245

    申请日：2019-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Paolo Amato

    IPC: G06F3/06 ,  G06F11/07

    Abstract: An apparatus can have an array of memory cells and a controller coupled to the array. The controller can be configured to read a group sentinel cells of the array and without reading a number of other groups of cells of the array to determine that data stored in the number of other groups of cells lacks integrity based on a determination that data stored in the group of sentinel cells lacks integrity.

    DATA RELOCATION IN HYBRID MEMORY
    119.
    发明申请
    DATA RELOCATION IN HYBRID MEMORY 审中-公开

    公开(公告)号：US20200233585A1

    公开(公告)日：2020-07-23

    申请号：US16839721

    申请日：2020-04-03

    Applicant: Micron Technology, Inc.

    Inventor： Emanuele Confalonieri ,  Marco Dallabora ,  Paolo Amato ,  Danilo Caraccio ,  Daniele Balluchi

    IPC: G06F3/06 ,  G11C11/00 ,  G11C13/00 ,  G11C16/26

    Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.

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