公开(公告)号：US07689891B2

公开(公告)日：2010-03-30

申请号：US11225640

申请日：2005-09-13

申请人： Robert H. Bell, Jr. ,  Guy L. Guthrie ,  William J. Starke

发明人： Robert H. Bell, Jr. ,  Guy L. Guthrie ,  William J. Starke

IPC分类号： G11C29/00

CPC分类号： G06F11/1064

摘要： A method of handling a stuck bit in a directory of a cache memory which detects an error in a stored tag having an address field, a state field and an error-correction field, determines that the error is associated with a stuck bit of the directory member, marks the directory member as defective, and casts out corrected address information. The error is detected during processing of a cache directory access request, and is determined to be associated with a stuck bit of the directory member by attempting to correct a first error and then detecting a second error after the first correction attempt. The address information is cast out by routing a surrogate tag contained in a surrogate member of the cache directory through error-correction pipeline circuitry while transmitting the address information from the surrogate member to a cast-out machine.

摘要翻译： 一种处理高速缓冲存储器的目录中的卡住位的方法，该高速缓冲存储器的目录中检测到具有地址字段，状态字段和纠错字段的存储标签中的错误，确定该错误与该目录的卡住位相关联 会员，将目录成员标记为有缺陷，并丢弃修正的地址信息。 在处理高速缓存目录访问请求期间检测到错误，并且通过尝试校正第一错误然后在第一次校正尝试之后检测第二错误来确定与目录成员的卡住位相关联。 通过错误校正流水线电路路由包含在高速缓存目录的代理成员中的代理标签，同时将地址信息从代理成员发送到投放机器，来丢弃地址信息。

公开(公告)号：US20090198933A1

公开(公告)日：2009-08-06

申请号：US12024181

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke

IPC分类号： G06F12/14

CPC分类号： G06F9/526

摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.

摘要翻译： 公开了一种在多处理器系统内处理多个存储器请求的方法。 锁控制部分最初被分配给系统存储器内的数据块。 响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。 如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。 如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。 然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。

公开(公告)号：US07533321B2

公开(公告)日：2009-05-12

申请号：US11225570

申请日：2005-09-13

申请人： Robert H. Bell, Jr. ,  Guy L. Guthrie ,  William J. Starke

发明人： Robert H. Bell, Jr. ,  Guy L. Guthrie ,  William J. Starke

IPC分类号： G11C29/00

CPC分类号： G11C29/832 ,  G06F11/1064

摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.

摘要翻译： 一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段 ，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员 的目录成员中的卡住位。 多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码 。 还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。

公开(公告)号：US08645627B2

公开(公告)日：2014-02-04

申请号：US13447462

申请日：2012-04-16

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0888 ,  Y02D10/13

摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.

摘要翻译： 数据处理系统包括包括最低级高速缓存，耦合到多级高速缓存层级的处理器核心以及耦合到最低级高速缓存和存储器系统存储器的存储器总线的存储器控​​制器的多级高速缓存层级。 存储器控制器包括物理读取队列，其缓冲通过存储器总线从系统存储器读取的数据，以及物理写入队列，其通过存储器总线缓冲要写入系统存储器的数据。 存储器控制器基于最低级高速缓冲存储器中的多个脏高速缓存线，对存储器总线上的读操作授予优先级。

公开(公告)号：US08521982B2

公开(公告)日：2013-08-27

申请号：US12424207

申请日：2009-04-15

申请人： Robert A. Cargnoni ,  Guy L. Guthrie ,  Thomas L. Jeremiah ,  Stephen J. Powell ,  William J. Starke ,  Jeffrey A. Steucheli

发明人： Robert A. Cargnoni ,  Guy L. Guthrie ,  Thomas L. Jeremiah ,  Stephen J. Powell ,  William J. Starke ,  Jeffrey A. Steucheli

IPC分类号： G06F12/00

CPC分类号： G06F12/123 ,  G06F12/084 ,  G06F12/0897

摘要： A system and method for tracking core load requests and providing arbitration and ordering of requests. When a core interface unit (CIU) receives a load operation from the processor core, a new entry in allocated in a queue of the CIU. In response to allocating the new entry in the queue, the CIU detects contention between the load request and another memory access request. In response to detecting contention, the load request may be suspended until the contention is resolved. Received load requests may be stored in the queue and tracked using a least recently used (LRU) mechanism. The load request may then be processed when the load request resides in a least recently used entry in the load request queue. CIU may also suspend issuing an instruction unless a read claim (RC) machine is available. In another embodiment, CIU may issue stored load requests in a specific priority order.

摘要翻译： 用于跟踪核心负载请求并提供仲裁和请求排序的系统和方法。 当核心接口单元（CIU）从处理器核心接收到加载操作时，分配在CIU队列中的新条目。 响应于在队列中分配新条目，CIU检测加载请求和另一个存储器访问请求之间的争用。 响应于检测到争用，负载请求可以被暂停，直到争用被解决。 接收到的加载请求可以存储在队列中，并使用最近最少使用的（LRU）机制进行跟踪。 然后可以在加载请求驻留在加载请求队列中最近最少使用的条目中时处理加载请求。 除非读取权利要求（RC）机器可用，否则CIU也可以暂停发出指令。 在另一个实施例中，CIU可以以特定优先级顺序发布存储的加载请求。

公开(公告)号：US08140770B2

公开(公告)日：2012-03-20

申请号：US11054886

申请日：2005-02-10

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0844 ,  G06F12/0817 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

摘要翻译： 高速缓存一致数据处理系统至少包括耦合用于通信的第一和第二相干域。 第一和第二相关域各自包括第一和第二高速缓存存储器中的相应一个。 第一相关域中的主机至少部分地基于类型，从包括第一相关域的第一范围和包括第一和第二相干域两者的第二范围中选择操作的初始广播的范围 的操作。 然后，主机使用所选择的范围在高速缓存相干数据处理系统内执行操作的初始广播。

公开(公告)号：US07454580B2

公开(公告)日：2008-11-18

申请号：US11380020

申请日：2006-04-25

申请人： Ravi K. Arimilli ,  Thomas M. Capasso ,  Robert A. Cargnoni ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke

发明人： Ravi K. Arimilli ,  Thomas M. Capasso ,  Robert A. Cargnoni ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/544

摘要： A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.

摘要翻译： 数据处理系统包括处理器核心和存储器子系统。 存储器子系统包括具有多个条目的存储队列，其中每个条目包括用于保存存储操作的目标地址的地址字段，用于保存用于存储操作的数据的数据字段和指示存在或不存在的虚拟同步字段 与该条目相关联的同步操作。 存储器子系统还包括存储队列控制器，其响应于在存储器子系统处的接收包括同步操作和特定存储操作的一系列操作，将特定存储操作的目标地址和数据放置在地址字段和数据中 字段，并且设置条目的虚拟同步字段以表示同步操作，使得减少使用的存储队列条目的数量。

公开(公告)号：US20080225863A1

公开(公告)日：2008-09-18

申请号：US12124639

申请日：2008-05-21

申请人： Ravi K. Arimilli ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  Praveen S. Reddy ,  William J. Starke

发明人： Ravi K. Arimilli ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  Praveen S. Reddy ,  William J. Starke

IPC分类号： H04L12/56

CPC分类号： G06F15/16

摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.

摘要翻译： 数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元， 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。

公开(公告)号：US08838901B2

公开(公告)日：2014-09-16

申请号：US12775510

申请日：2010-05-07

申请人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： David M. Daly ,  Benjiman L. Goodman ,  Hillery C. Hunter ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0817 ,  G06F12/0897 ,  Y02D10/13

摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.

摘要翻译： 数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。 高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。 存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。 存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

公开(公告)号：US08139592B2

公开(公告)日：2012-03-20

申请号：US12124524

申请日：2008-05-21

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Benjiman L. Goodman ,  William J. Starke ,  Jeffrey A. Stuecheli

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Benjiman L. Goodman ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC分类号： H04L12/28 ,  H04L12/56 ,  G06F13/00 ,  G06F13/28 ,  H04H20/71

CPC分类号： G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.

摘要翻译： 数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送 处理单位。 该通信包括具有请求的操作和表示对请求的系统响应的组合响应。 至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列 在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。 票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。