Method for protecting sidewalls of etched openings to prevent via poisoning
    111.
    发明授权
    Method for protecting sidewalls of etched openings to prevent via poisoning 有权
    用于保护蚀刻开口的侧壁以防止通过中毒的方法

    公开(公告)号:US06602780B2

    公开(公告)日:2003-08-05

    申请号:US09947788

    申请日:2001-09-06

    IPC分类号: H01L214763

    摘要: A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.

    摘要翻译: 一种用于形成保护性氧化物衬垫以减少表面反射率的方法,包括在导电层上提供亲水性绝缘层; 在所述亲水绝缘层上提供抗反射涂层(ARC)层; 在抗反射涂层(ARC)层上提供蚀刻停止层; 在蚀刻停止层的表面上光刻地限定图案用于蚀刻; 各向异性蚀刻至少一个至少部分延伸穿过亲水性绝缘层的厚度的蚀刻开口; 沉积氧化物衬里,使得所述至少一个蚀刻开口和所述表面的侧壁和底部被所述氧化物衬垫覆盖; 并且根据化学机械(CMP)工艺将氧化物衬垫从辅助表面去除到表面反射率。

    Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer
    112.
    发明授权
    Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer 有权
    采用碳掺杂氧化硅平面化停止层形成低介电常数镶嵌结构的方法

    公开(公告)号:US06602779B1

    公开(公告)日:2003-08-05

    申请号:US10144522

    申请日:2002-05-13

    IPC分类号: H01L214763

    摘要: Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a hard mask layer formed upon the dielectric layer. The hard mask layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency power of from about 100 to about 500 watts per square centimeter substrate area. The hard mask layer provides for attenuated abrasive damage to the dielectric layer.

    摘要翻译: 在用于形成介于其图案之间的图案化导体层的镶嵌方法中,由相对较低的介电常数介电材料法形成的电介质层,采用在该介电层上形成的硬掩模层。 使用等离子体增强化学气相沉积(PECVD)方法依次使用有机硅烷碳和硅源材料,基板温度为约200至约500摄氏度,射频功率为约100至 约500瓦/平方厘米基板面积。 硬掩模层为介电层提供减弱的磨损损伤。