利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

118 条记录 (耗时 0.031 秒)

    Method for protecting sidewalls of etched openings to prevent via poisoning
    1.
    发明授权
    Method for protecting sidewalls of etched openings to prevent via poisoning 有权
    用于保护蚀刻开口的侧壁以防止通过中毒的方法

    公开(公告)号：US06602780B2

    公开(公告)日：2003-08-05

    申请号：US09947788

    申请日：2001-09-06

    申请人： Tsu Shih ,  Yung-Cheng Lu ,  Lih Ping Li ,  Tien-I Bao ,  Chung Chi Ko

    发明人： Tsu Shih ,  Yung-Cheng Lu ,  Lih Ping Li ,  Tien-I Bao ,  Chung Chi Ko

    IPC分类号： H01L214763

    CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L2221/1057

    摘要： A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.

    摘要翻译： 一种用于形成保护性氧化物衬垫以减少表面反射率的方法，包括在导电层上提供亲水性绝缘层; 在所述亲水绝缘层上提供抗反射涂层（ARC）层; 在抗反射涂层（ARC）层上提供蚀刻停止层; 在蚀刻停止层的表面上光刻地限定图案用于蚀刻; 各向异性蚀刻至少一个至少部分延伸穿过亲水性绝缘层的厚度的蚀刻开口; 沉积氧化物衬里，使得所述至少一个蚀刻开口和所述表面的侧壁和底部被所述氧化物衬垫覆盖; 并且根据化学机械（CMP）工艺将氧化物衬垫从辅助表面去除到表面反射率。

    SiOCH low k surface protection layer formation by CxHy gas plasma treatment
    5.
    发明授权
    SiOCH low k surface protection layer formation by CxHy gas plasma treatment 有权
    SiOCH低k表面保护层通过CxHy气体等离子体处理形成

    公开(公告)号：US06962869B1

    公开(公告)日：2005-11-08

    申请号：US10270974

    申请日：2002-10-15

    申请人： Tien-I Bao ,  Hsin-Hsien Lu ,  Lih-Ping Li ,  Chung-Chi Ko ,  Aaron Song ,  Syun-Ming Jang

    发明人： Tien-I Bao ,  Hsin-Hsien Lu ,  Lih-Ping Li ,  Chung-Chi Ko ,  Aaron Song ,  Syun-Ming Jang

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/3105 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835

    摘要： A method of protecting a low k dielectric layer that is preferably comprised of a material containing Si, O, C, and H is described. The dielectric layer is subjected to a gas plasma that is generated from a CXHY gas which is preferably ethylene. Optionally, hydrogen may be added to the CXHY gas. Another alternative is a two step plasma process involving a first plasma treatment of CXHY or CXHY combined with H2 and a second plasma treatment with H2. The modified dielectric layer provides improved adhesion to anti-reflective layers and to a barrier metal layer in a damascene process. The modified dielectric layer also has a low CMP rate that prevents scratch defects and an oxide recess from occurring next to the metal layer on the surface of the damascene stack. The plasma treatments are preferably done in the same chamber in which the dielectric layer is deposited.

    摘要翻译： 描述了保护低k电介质层的方法，其优选由含有Si，O，C和H的材料组成。 对电介质层进行气化等离子体，该等离子体是由优选乙烯的C X H Y气产生的。 任选地，可以将氢气加入到C 1 H 2 H 2 O气体中。 另一种替代方案是涉及第一等离子体处理C X> Y Y or SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB >与H 2 H 2结合，并且与H 2 2进行第二等离子体处理。 改进的介电层在镶嵌工艺中提供对抗反射层和阻挡金属层的改善的粘合性。 改进的介电层也具有低CMP速率，其防止划痕缺陷和氧化物凹陷在镶嵌层的表面上邻近金属层发生。 等离子体处理优选在沉积介电层的相同的室中进行。

    Method for forming a carbon doped oxide low-k insulating layer
    6.
    发明授权
    Method for forming a carbon doped oxide low-k insulating layer 有权
    形成碳掺杂氧化物低k绝缘层的方法

    公开(公告)号：US06812043B2

    公开(公告)日：2004-11-02

    申请号：US10131713

    申请日：2002-04-25

    申请人： Tien-I Bao ,  Chung-Chi Ko ,  Lih-Ping Li ,  Syun-Ming Jang

    发明人： Tien-I Bao ,  Chung-Chi Ko ,  Lih-Ping Li ,  Syun-Ming Jang

    IPC分类号： H01L2100

    CPC分类号： H01L21/76826 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76807

    摘要： A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.

    摘要翻译： 一种用于半导体器件制造的具有降低的介电常数和增加的硬度的介电绝缘层的形成方法，包括提供具有在其上形成电介质绝缘层的工艺表面的半导体晶片; 根据CVD工艺沉积碳掺杂氧化物层的CVD工艺，其包括具有Si-O基团和Si-Ry基团的牛至硅烷前体，其中R是烷基或环烷基，y是与 硅; 并且将碳掺杂的氧化物层暴露于氢等离子体处理一段时间，从而减少碳掺杂的氧化物层厚度，包括减少碳掺杂的氧化物层介电常数并增加碳掺杂的氧化物层的硬度。

    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
    9.
    发明授权
    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
    包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例

    公开(公告)号：US07723226B2

    公开(公告)日：2010-05-25

    申请号：US11654427

    申请日：2007-01-17

    申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

    摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

    Method for ultra low-K dielectric deposition
    10.
    发明申请
    Method for ultra low-K dielectric deposition 审中-公开
    超低K电介质沉积方法

    公开(公告)号：US20050048795A1

    公开(公告)日：2005-03-03

    申请号：US10649566

    申请日：2003-08-27

    申请人： Chung-Chi Ko ,  Yung-Cheng Lu ,  Tien-I Bao ,  Hui-Lin Chang ,  Syun-Ming Jang

    发明人： Chung-Chi Ko ,  Yung-Cheng Lu ,  Tien-I Bao ,  Hui-Lin Chang ,  Syun-Ming Jang

    IPC分类号： H01L21/312 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02271 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/7682

    摘要： The present invention provides a method of forming a semiconductor structure having an ultra low-K dielectric material that adheres well to the substrate. The method includes depositing a low-K material on the top surface of a substrate at a low temperature of no more than 250° by a CVD or spin-on process. The dielectric material is then cured by placing the substrate with the dielectric film in an environment where the temperature is regulated at about 400° or less as the dielectric film is being subjected to a plasma treatment or an E-beam treatment or UV treatment. The environment may further include one or more gases or a mixture of gases selected from the group consisting of H2, N2, NH3, CO2, all hydride gases and a mixture of these gases.

    摘要翻译： 本发明提供一种形成半导体结构的方法，所述半导体结构具有与基底良好粘合的超低K电介质材料。 该方法包括通过CVD或旋涂工艺在低于250°的低温下在衬底的顶表面上沉积低K材料。 然后通过将介质膜放置在介质膜经受等离子体处理或电子束处理或UV处理的温度调节在约400°或更小的环境中来固化电介质材料。 环境可以进一步包括选自H 2，N 2，NH 3，CO 2，所有氢化物气体和这些气体的混合物的一种或多种气体或气体混合物。