公开(公告)号：US10128193B2

公开(公告)日：2018-11-13

申请号：US15413690

申请日：2017-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L21/4763 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

Abstract: A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.

公开(公告)号：US20180308787A1

公开(公告)日：2018-10-25

申请号：US15491986

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/82

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has at least one chip, through interlayer vias aside the chip and a composite molding compound encapsulating the chip and the through interlayer vias. The semiconductor package may further include a redistribution layer and conductive elements disposed on the redistribution layer.

公开(公告)号：US10014260B2

公开(公告)日：2018-07-03

申请号：US15347912

申请日：2016-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/29

Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.