公开(公告)号：US11955460B2

公开(公告)日：2024-04-09

申请号：US17063251

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Meng-Tse Chen ,  Sheng-Feng Weng ,  Sheng-Hsiang Chiu ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2224/0237 ,  H01L2224/024 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/06 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19102 ,  H01L2924/3511

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

公开(公告)号：US20200020634A1

公开(公告)日：2020-01-16

申请号：US16035713

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Tsung Tsai ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Sheng-Hsiang Chiu ,  Yi-Da Tsai

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065

Abstract: A package and a method of manufacturing the same are provided. The package includes a first die, a second die, a third die, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The third die is disposed on the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the third die and fills in a gap between the first die, the second die, and the third die. The RDL structure is disposed on the third die and the encapsulant.

公开(公告)号：US11075131B2

公开(公告)日：2021-07-27

申请号：US16547579

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Tsai-Tsung Tsai ,  Sheng-Chieh Yang ,  Chia-Min Lin

IPC: H01L23/29 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/532

Abstract: A semiconductor package including a semiconductor die, a molding compound and a redistribution structure is provided. The molding compound laterally wraps around the semiconductor die, wherein the molding compound includes a base material and a first filler particle and a second filler particle embedded in the base material. The first filler particle has a first recess located in a top surface of the first filler particle, and the second filler particle has at least one hollow void therein. The redistribution structure is disposed on the semiconductor die and the molding compound, wherein the redistribution structure has a polymer dielectric layer. The polymer dielectric layer includes a body portion and a first protruding portion protruding from the body portion, wherein the body portion is in contact with the base material and the top surface of the first filler particle, and the first protruding portion fits with the first recess of the first filler particle.

公开(公告)号：US10014260B2

公开(公告)日：2018-07-03

申请号：US15347912

申请日：2016-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/29

Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.

公开(公告)号：US20210057298A1

公开(公告)日：2021-02-25

申请号：US16547579

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Tsai-Tsung Tsai ,  Sheng-Chieh Yang ,  Chia-Min Lin

IPC: H01L23/29 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/56

Abstract: A semiconductor package including a semiconductor die, a molding compound and a redistribution structure is provided. The molding compound laterally wraps around the semiconductor die, wherein the molding compound includes a base material and a first filler particle and a second filler particle embedded in the base material.
The first filler particle has a first recess located in a top surface of the first filler particle, and the second filler particle has at least one hollow void therein. The redistribution structure is disposed on the semiconductor die and the molding compound, wherein the redistribution structure has a polymer dielectric layer. The polymer dielectric layer includes a body portion and a first protruding portion protruding from the body portion, wherein the body portion is in contact with the base material and the top surface of the first filler particle, and the first protruding portion fits with the first recess of the first filler particle.

公开(公告)号：US20210020611A1

公开(公告)日：2021-01-21

申请号：US17063251

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Meng-Tse Chen ,  Sheng-Feng Weng ,  Sheng-Hsiang Chiu ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

公开(公告)号：US10535609B2

公开(公告)日：2020-01-14

申请号：US16020030

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.