公开(公告)号：US06312988B1

公开(公告)日：2001-11-06

申请号：US09389532

申请日：1999-09-02

申请人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  D. Mark Durcan

发明人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  D. Mark Durcan

IPC分类号： H01L218242

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node. In yet another embodiment, a plurality of capacitor storage nodes are formed arranged in columns. A common cell electrode layer is formed over the plurality of capacitor storage nodes. Cell electrode layer material is removed from between the columns and isolates individual cell electrodes over individual respective capacitor storage nodes. After the removing of the cell electrode layer material, conductive material is formed over portions of remaining cell electrode material thereby placing some of the individual cell electrodes into electrical communication with one another.

摘要翻译： 描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。 在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。 随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。 在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。 在另一个实施例中，电容器存储节点形成为具有与其接合的最上表面和侧表面。 在最大表面上形成保护帽，并且在侧表面和保护盖上形成电容器电介质层。 在电容器存储节点的侧表面上形成电池电极层。 在另一个实施例中，形成多列电容器存储节点。 在多个电容器存储节点上形成公共电极电极层。 从柱之间移除电极电极层材料，并在各个电容器存储节点上隔离各个电池电极。 在除去电池电极层材料之后，在剩余的电池电极材料的部分上形成导电材料，从而使一些单个电池电极彼此电连通。

公开(公告)号：US08563229B2

公开(公告)日：2013-10-22

申请号：US11831012

申请日：2007-07-31

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： G03F7/20

CPC分类号： H01L21/0274 ,  H01L21/0337

摘要： Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The deposited negative photoresist layer is patterned, thereby removing photoresist from between the spacers in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers is facilitated. The pattern defined by the spacers and the patterned negative photoresist is transferred to one or more underlying masking layers before being transferred to a substrate.

摘要翻译： 间隔通过间距倍增形成，并且负光致抗蚀剂层沉积在间隔物上和上​​方以形成附加的掩模特征。 图案化沉积的负性光致抗蚀剂层，从而在一些区域中从间隔物之间​​除去光致抗蚀剂。 在图案化期间，不需要将光引导到需要负光致抗蚀剂去除的区域，并且促进从间隔物之间​​清洁去除负光致抗蚀剂。 由间隔物和图案化的负性光致抗蚀剂限定的图案在转移到基底之前转移到一个或多个下面的掩蔽层。

公开(公告)号：US08431971B2

公开(公告)日：2013-04-30

申请号：US13235722

申请日：2011-09-19

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/84

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L45/06 ,  H01L45/085 ,  H01L45/144 ,  H01L45/1683

摘要： Crisscrossing spacers formed by pitch multiplication are used to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with conductive material to form conductive contacts.

摘要翻译： 通过间距倍增形成的交叉式间隔物用于形成隔离特征，例如接触孔。 在第一层上形成第一多个心轴，并且围绕每个心轴形成第一多个间隔件。 在第一级上方的第二级上形成第二多个心轴。 当从俯视图看时，形成第二多个心轴使得它们穿过第一多个心轴。 围绕第二多个心轴的每一个形成第二多个间隔件。 选择性地去除第一和第二心轴以留下由交叉的第一和第二多个间隔物限定的空隙图案。 这些间隔物可以用作掩模以将空隙的图案转移到基底。 空隙可以用导电材料填充以形成导电接触。

公开(公告)号：US08243527B2

公开(公告)日：2012-08-14

申请号：US13209704

申请日：2011-08-15

申请人： Chih-Wei Hung ,  Chia-Ta Hsieh ,  Luan C. Tran

发明人： Chih-Wei Hung ,  Chia-Ta Hsieh ,  Luan C. Tran

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0441 ,  H03K19/1776

摘要： A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful.

摘要翻译： 非易失性存储器件包括耦合到位线和字线的第一金属氧化物半导体（CMOS）器件和耦合到第一CMOS器件的第二CMOS器件。 第二CMOS器件还耦合到互补位线和互补字线。 第一和第二CMOS器件彼此互补。 输出节点耦合在第一CMOS器件和第二CMOS器件之间。 编程非易失性现场可编程门阵列（NV-FPGA）的方法包括将信息处理系统耦合到FPGA，对FPGA中的多个存储单元进行块擦除，验证块擦除成功，编程 FPGA的上一页，验证上页编程是否成功，编写FPGA的下一页，并验证下页编程是否成功。

公开(公告)号：US20100317193A1

公开(公告)日：2010-12-16

申请号：US12850511

申请日：2010-08-04

申请人： Luan C. Tran ,  John Lee ,  Zengtao Tony Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan C. Tran ,  John Lee ,  Zengtao Tony Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/768 ,  H01L21/302

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

摘要翻译： 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

公开(公告)号：US20100264482A1

公开(公告)日：2010-10-21

申请号：US12829904

申请日：2010-07-02

申请人： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

发明人： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

摘要： Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.

摘要翻译： 存储单元包括控制栅极，电荷捕获材料和控制栅极与电荷捕获材料之间的电荷阻挡材料。 电荷阻挡材料被配置为允许通过从控制栅极到电荷捕获材料的孔的增强的F-N隧穿来擦除存储器单元。

公开(公告)号：US07759197B2

公开(公告)日：2010-07-20

申请号：US11219067

申请日：2005-09-01

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/84

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L45/06 ,  H01L45/085 ,  H01L45/144 ,  H01L45/1683

摘要： Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross, e.g., are orthogonal to, the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with material, e.g., conductive material, to form conductive contacts.

摘要翻译： 用螺距倍增形成的交叉式间隔物用作掩模以形成隔离特征，例如接触孔。 在第一层上形成第一多个心轴，并且围绕每个心轴形成第一多个间隔件。 在第一级上方的第二级上形成第二多个心轴。 当从俯视图看时，第二多个心轴形成为使得它们与第一多个心轴交叉，例如正交。 围绕第二多个心轴的每一个形成第二多个间隔件。 选择性地去除第一和第二心轴以留下由交叉的第一和第二多个间隔物限定的空隙图案。 这些间隔物可以用作掩模以将空隙的图案转移到基底。 空隙可以填充材料，例如导电材料，以形成导电接触。

公开(公告)号：US07749848B2

公开(公告)日：2010-07-06

申请号：US11900595

申请日：2007-09-12

申请人： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

发明人： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

摘要： Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

摘要翻译： 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。

公开(公告)号：US07538036B2

公开(公告)日：2009-05-26

申请号：US11216759

申请日：2005-08-31

申请人： Brett W. Busch ,  Luan C. Tran ,  Ardavan Niroomand ,  Fred D. Fishburn ,  Yoshiki Hishiro ,  Ulrich C. Boettiger ,  Richard D. Holscher

发明人： Brett W. Busch ,  Luan C. Tran ,  Ardavan Niroomand ,  Fred D. Fishburn ,  Yoshiki Hishiro ,  Ulrich C. Boettiger ,  Richard D. Holscher

IPC分类号： H01L21/3205

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/10852 ,  H01L28/91 ,  Y10S438/942 ,  Y10S438/946

摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

摘要翻译： 图案化掩模可以如下形成。 在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。 第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。 随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。 组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。 图案化掩模可以用于在掩模下面的衬底中形成图案。 形成在基板中的图案可以对应于电容器容器开口的阵列。 可以在开口内形成电容结构。 电容器结构可以并入DRAM阵列中。

公开(公告)号：US07449390B2

公开(公告)日：2008-11-11

申请号：US11137269

申请日：2005-05-24

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/331

CPC分类号： H01L27/10852 ,  G11C11/24 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10855

摘要： Methods of forming memory are described. According to one arrangement, a method of forming memory includes forming a plurality of word lines over a substrate, the word lines having insulating material thereover, forming a plurality of bit lines over the word lines, the bit lines having insulating material thereover, forming insulative material over the word lines and the bit lines, the insulative material being etchably different from the insulating material over the word lines and the insulating material over the bit lines, and selectively etching contact openings through the insulative material relative to the insulating material over the bit lines and the insulating material over the word lines, the openings being self-aligned to both the bit lines and word lines and extending to proximate the substrate.

摘要翻译： 描述形成记忆的方法。 根据一种结构，形成存储器的方法包括在衬底上形成多个字线，字线在其上具有绝缘材料，在字线之上形成多个位线，位线在其上具有绝缘材料，形成绝缘 在字线和位线之间的材料，绝缘材料可以与字线上的绝缘材料和位线上的绝缘材料可蚀刻地不同，并且通过绝缘材料相对于绝缘材料选择性地蚀刻穿过绝缘材料的接触开口 线和绝缘材料在字线上，开口自对准到位线和字线并且延伸到靠近衬底。