公开(公告)号：US11567666B2

公开(公告)日：2023-01-31

申请号：US17211036

申请日：2021-03-24

Applicant: ATI Technologies ULC

Inventor： Philip Ng ,  Nippon Raval

IPC: G06F3/06

Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.

公开(公告)号：US11561797B2

公开(公告)日：2023-01-24

申请号：US16544594

申请日：2019-08-19

Applicant: ATI Technologies ULC

Inventor： Vinay Patel

IPC: H03M7/34 ,  G06F9/38 ,  H03M7/30 ,  H03M7/40

Abstract: An electronic device that includes a decompression engine that includes N decoders and a decompressor decompresses compressed input data that includes N streams of data. Upon receiving a command to decompress compressed input data, the decompression engine causes each of the N decoders to decode a respective one of the N streams from the compressed input data separately and substantially in parallel with others of the N decoders. Each decoder outputs a stream of decoded data of a respective type for generating commands associated with a compression standard for decompressing the compressed input data. The decompressor next generates, from the streams of decoded data output by the N decoders, commands for decompressing the data using the compression standard to recreate the original data. The decompressor next executes the commands to recreate the original data and stores the original data in a memory or provides the original data to another entity.

公开(公告)号：US11552892B2

公开(公告)日：2023-01-10

申请号：US16557914

申请日：2019-08-30

Applicant: ATI Technologies ULC

Inventor： Alexander S. Duenas

IPC: H04L47/10 ,  G06F13/38 ,  H04L47/24

Abstract: An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.

公开(公告)号：US11550722B2

公开(公告)日：2023-01-10

申请号：US17189844

申请日：2021-03-02

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Philip Ng ,  Nippon Raval ,  BuHeng Xu ,  Rostislav S. Dobrin ,  Shawn Han

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/02 ,  G06F13/24 ,  G06F13/16 ,  G06F12/1009

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.

公开(公告)号：US11533204B2

公开(公告)日：2022-12-20

申请号：US17121221

申请日：2020-12-14

Applicant: ATI Technologies ULC

Inventor： Saman Asgaran

IPC: H04L25/03 ,  H04B1/16 ,  G06F13/16 ,  H03F3/19

Abstract: A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ⅔ of the data rate.

公开(公告)号：US11521293B2

公开(公告)日：2022-12-06

申请号：US16943637

申请日：2020-07-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Guennadi Riguer ,  Brian K. Bennett

IPC: G06F3/06 ,  G06T1/60 ,  G06F9/54 ,  G06F9/50 ,  G06F12/02 ,  G06T1/20 ,  G09G5/36

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

公开(公告)号：US11490127B2

公开(公告)日：2022-11-01

申请号：US17139372

申请日：2020-12-31

Applicant: ATI Technologies ULC

Inventor： Wei Gao ,  Ihab Amer ,  Feng Pan ,  Mingkai Shao ,  Crystal Sau ,  Dong Liu ,  Gabor Sines ,  Yang Liu

IPC: H04N19/90 ,  H04N19/154

Abstract: Methods and apparatus provide cloud-based video encoding that generates encoded video data by one or more encoders in a cloud platform for a plurality of cloud encoding sessions. The methods and apparatus generate operational improvement tradeoff data in response to operational encoding metrics associated with the one or more encoders and change operational characteristics of the one or more encoders for at least one of the cloud encoding sessions based on the operational improvement tradeoff data.

公开(公告)号：US11488349B2

公开(公告)日：2022-11-01

申请号：US16455947

申请日：2019-06-28

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I.J. Glen ,  Keith Lee

IPC: G06T15/50 ,  G06T7/90 ,  G06T11/00

Abstract: In some examples, an apparatus obtains source layer pixels, such as those of a content image and first destination layer pixels, such as those of a destination image. The first destination layer pixels have associated alpha values. The apparatus obtains information that indicates a first blending color format for the alpha values. The first blending color format is different from a first destination layer color format for the first destination layer pixels and an output color format for a display. The apparatus converts the source and/or first destination layer pixels to the first blending color format. The apparatus generates first alpha blended pixels based on alpha blending the source layer pixels with the first destination layer pixels using the associated alpha values. The apparatus provides, for display on the display, the first alpha blended pixels.

公开(公告)号：US11469212B2

公开(公告)日：2022-10-11

申请号：US15247259

申请日：2016-08-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Bryan Black ,  Michael Z. Su ,  Gamal Refai-Ahmed ,  Joe Siegel ,  Seth Prejean

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

公开(公告)号：US20220308756A1

公开(公告)日：2022-09-29

申请号：US17214686

申请日：2021-03-26

Applicant: ATI Technologies ULC

Inventor： Nippon Raval ,  Philip Ng

IPC: G06F3/06

Abstract: An electronic device includes an input-output memory management unit (IOMMU). The IOMMU receives, from an input-output device, a memory access request directed to a given page of memory. The IOMMU then determines a particular encryption key from among a plurality of encryption keys associated with an owning entity to which the given page of memory is assigned. The IOMMU next communicates, to a encryption functional block, a specification of the particular encryption key to be used for encryption-related operations for processing the memory access request.