公开(公告)号：US5398328A

公开(公告)日：1995-03-14

申请号：US127105

申请日：1983-09-27

Applicant: Larry B. Weber ,  Earl A. Killian ,  Mark I. Himelstein

Inventor： Larry B. Weber ,  Earl A. Killian ,  Mark I. Himelstein

IPC: G06F9/06 ,  G06F5/00 ,  G06F7/76 ,  G06F9/34 ,  G06F9/44 ,  G06F9/455 ,  G06F12/04 ,  G06F7/00

CPC classification number: G06F7/768 ,  G06F9/34

Abstract: A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in conjunction with an XOR gate which couples the byte address to binary 3. The conversion method and apparatus is implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and XORing the two least significant bits of the byte address with a binary 3.

Abstract translation: 提供了一种使计算机能够使用大端或小端结构运行的方法和装置。 该方法和装置使用以下事实：将具有二进制3的一个架构中的字节地址的低两位进行异或将该字节地址转换为另一架构中的等效字节地址。 转换方法和装置通过在状态寄存器中设置指示大端或小端结构的位与X字门相结合来实现，该异或门将字节地址耦合到二进制3.转换方法和装置以软件方式 扫描输入的指令以进行加载和存储指令。 软件通过读取寄存器的内容并用二进制3异或字节地址的两个最低有效位来修改指令。

公开(公告)号：US5319763A

公开(公告)日：1994-06-07

申请号：US679463

申请日：1991-04-02

Applicant: Yui K. Ho ,  William C. Moyer ,  Joseph A. Gutierrez

Inventor： Yui K. Ho ,  William C. Moyer ,  Joseph A. Gutierrez

IPC: G06F7/00 ,  G06F7/76 ,  G06F9/308 ,  G06F11/28 ,  G06F15/82 ,  G06F9/22 ,  G06F9/26 ,  G06F11/18 ,  G06F13/30

CPC classification number: G06F9/30018

Abstract: A data processing system (10) implements a static and a dynamic masking operation of operand information concurrently. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are concurrently implemented using a specialized bit cell (60) contained in both the breakpoint register (24) and the CAM array (26). The specialized bit cell (60) is comprised of two transistors (62 and 64) to concurrently mask a respective bit of operand information during a comparison operation.

Abstract translation: 数据处理系统（10）同时实现操作数信息的静态和动态屏蔽操作。 静态掩码实现由用户指定的预定数量的比特的条件掩码，并且在存储在断点寄存器（24）中的断点地址与通过逻辑地址总线（11）传送的逻辑地址之间的比较操作之前确定， 。 动态掩码值实现一个可变掩码，允许数据处理系统根据断点地址访问的大小屏蔽断点地址。 使用包含在断点寄存器（24）和CAM阵列（26）中的专用位单元（60）同时实现静态掩码值和动态掩码值。 专用位单元（60）由两个晶体管（62和64）组成，以在比较操作期间同时屏蔽操作数​​信息的相应位。

公开(公告)号：US5303175A

公开(公告)日：1994-04-12

申请号：US98984

申请日：1993-07-29

Applicant: Hiroaki Suzuki

Inventor： Hiroaki Suzuki

IPC: G06F7/00 ,  G06F7/38 ,  G06F7/483 ,  G06F7/57 ,  G06F7/76

CPC classification number: G06F7/483 ,  G06F2207/382 ,  G06F7/49936 ,  G06F7/49963

Abstract: The number of zeroes in an operation result of 54 bits is counted by a priority encoder 2 on a three-bit basis. A 54.times.18 normalization shifter 3 normalizes the operation result in response to the counted result. An LSB determination logic 4 determines a position of the LSB shifted by overflow and underflow, according to a logic state of the most significant three bits of the operation result, and an increment signal generating portion 5 and a three-bit input incrementer 6 add 1 corresponding to the shifted LSB to generate a round-up signal. A 54.times.3 normalization shifter 9 selectively normalizes a processed result of a lost-significant bit processing portion B or that of a round processing portion A. Normalization shifters of the lost-significant bit processing portion constitute a two stage structure, in which the normalization shifter in the final stage also serves for the rounding processing portion, and a normalization shifter in the succeeding stage of an arithmetic operation portion is omitted. Consequently, a floating point arithmetic unit with the reduced volume of hardware can be provided without reducing the operation speed.

Abstract translation: 54比特的运算结果中的零数由优先编码器2以三比特为基础进行计数。 54 * 18归一化移位器3根据计数结果对运算结果进行归一化。 LSB确定逻辑4根据运算结果的最高有效三位的逻辑状态来确定移位了溢出和下溢的LSB的位置，并且增量信号产生部分5和三位输入增量器6加1 对应于移位的LSB以产生向上舍入信号。 54 * 3归一化移位器9有选择地对丢失有效位处理部分B或圆形处理部分A的处理结果进行归一化。丢失有效位处理部分的归一化移位器构成两阶段结构，其中归一化 最终级的移位器也用于舍入处理部分，并且省略了算术运算部分的后级的归一化移位器。 因此，可以提供具有减小的硬件体积的浮点算术单元，而不降低操作速度。

公开(公告)号：US5204825A

公开(公告)日：1993-04-20

申请号：US751931

申请日：1991-08-30

Applicant: Kenneth Ng

Inventor： Kenneth Ng

IPC: G06F7/00 ,  G06F7/42 ,  G06F7/485 ,  G06F7/74 ,  G06F7/76

CPC classification number: G06F7/74

Abstract: A leading zero predictor (LZP) in parallel with the full subtraction operation correctly predicts the exact number of leading zeros of a subtraction result. Once the full subtraction operation is completed, the necessary shifts may be performed immediately, without a delay to determine the presence of leading zeros, and without need for a normalization corrector.

Abstract translation: 与完全减法操作并行的前导零预测器（LZP）正确地预测减法结果的前导零的确切数量。 一旦完全减法操作完成，则可以立即执行必要的移位，而不需要延迟来确定前导零的存在，并且不需要归一化校正器。

公开(公告)号：US5191335A

公开(公告)日：1993-03-02

申请号：US612726

申请日：1990-11-13

Applicant: Jerald E. Leitherer

Inventor： Jerald E. Leitherer

IPC: G06F7/00 ,  G06F7/76 ,  H03M7/24

CPC classification number: H03M7/24

Abstract: The anomaly handling facility provides a system for controlling conversion, detecting anomalies, providing analysis of anomaly content in an array of floating-point elements, and preserving reconstruction data to recover value accuracy typically lost when anomalies are encountered during conversion.Although the preferred embodiment specifically handles anomalies relative to the commonality of value representation by both IBM ESA/370 hexadecimal floating-point notations and ANSI/IEEE 754-1985 binary floating-point stand notations, the systematic design provided by the disclosed floating-point notation conversion anomaly handling facility can be applied to an pair of floating-point notation systems that are not totally coincident in value coverage.

公开(公告)号：US5182723A

公开(公告)日：1993-01-26

申请号：US767896

申请日：1991-09-30

Applicant: Masatsugu Kamimura

Inventor： Masatsugu Kamimura

IPC: G06F7/487 ,  G06C15/00 ,  G06F7/00 ,  G06F7/544 ,  G06F7/57 ,  G06F7/76 ,  G10H1/02 ,  H03H17/00 ,  H03H17/02 ,  H03H17/04

CPC classification number: G06F7/5443 ,  G06F7/483 ,  G06F7/49942

Abstract: A computing method of floating-point represented data including dividing data x with a n (n>M) bit length into high rank data X' and low rank data .alpha. with a mutual m bit length, a mantissa part of the high rank data X' leaving the same bits as those of the data x by k bits (k.gtoreq.1) from its initial bit to replace the rest of the bits of X' by zero, the low rank data .alpha. being formed as X--X', and computing other data together with the high rank data X' and the low rank data .alpha..

公开(公告)号：US5159690A

公开(公告)日：1992-10-27

申请号：US252391

申请日：1988-09-30

Applicant: Norman H. Margolus ,  Tommaso Toffoli

Inventor： Norman H. Margolus ,  Tommaso Toffoli

IPC: G06F7/76 ,  G06F15/173 ,  G06F15/80

CPC classification number: G06F7/762 ,  G06F15/17368 ,  G06F15/8023

Abstract: A method for coordinating the activity of a plurality of processors in a computing architecture adapted to emulate a physical space, in which spatial locality is reflected in memory organization, including the steps of subdividing the emulated physical space, assigning memory to each subdivision, and assigning a processor to each assigned memory, respectively. A related data array computer for performing an iterative updating operation upon data bits, including a first circuit for performing data-blind data movement upon the data bits, the circuBACKGROUND OF THE INVENTIONThe U.S. Government has non-exclusive rights in this invention pursuant to contract number N00014-84-K-0099 awarded by DARPA.

Abstract translation: 一种用于协调在适于模拟物理空间的计算架构中的多个处理器的活动的方法，其中空间位置反映在存储器组织中，包括以下步骤：细分仿真物理空间，将存储器分配给每个细分，以及分配 处理器分别分配给每个分配的存储器。 一种相关数据阵列计算机，用于对数据比特执行迭代更新操作，包括用于在数据比特上进行数据盲数据移动的第一电路，该电路是可扩展的，以及第二电路，用于至少执行任意更新功能 的数据位。 该架构适用于轻松实现细胞自动机。

公开(公告)号：US5144581A

公开(公告)日：1992-09-01

申请号：US471854

申请日：1990-01-29

Applicant: Akitoshi Toda ,  Ryouhei Shimizu ,  Hiroko Ohta ,  Hiroshi Kajimura ,  Yoshiyuki Mimura ,  Yasuo Isono ,  Toshihito Kouchi

Inventor： Akitoshi Toda ,  Ryouhei Shimizu ,  Hiroko Ohta ,  Hiroshi Kajimura ,  Yoshiyuki Mimura ,  Yasuo Isono ,  Toshihito Kouchi

IPC: G01N27/00 ,  G01Q60/10 ,  G06F5/01 ,  G06F5/10 ,  G06F7/76 ,  G06F7/78 ,  G11B9/00 ,  G11B27/19 ,  G11B27/30 ,  G11C11/21

CPC classification number: G06F7/785 ,  G06F5/01 ,  G06F5/10 ,  G06F7/768 ,  G11B27/19 ,  G11B27/3027 ,  G11B9/14 ,  G11B9/1418 ,  B82Y10/00 ,  G01Q80/00 ,  G06F2205/104 ,  G11B9/1481 ,  Y10S977/861 ,  Y10S977/947

Abstract: A micro scanning tunneling microscope ("STM") arithmetic circuit device comprises an information-rewritable micro STM recording medium and a micro STM recording apparatus which temporarily stores information on the recording medium such that the information can be read as a variation in a tunnel current. The recording apparatus has a probe (probes) for writing/reading information on the recording medium and a scanner for varying a relationship in position between the probe and the recording medium. The micro STM recording apparatus uses a recording medium having a specific format as the micro STM recording medium in which recorded information is read as a variation in a tunnel current. That is, the recording medium has an address area in which address information is recorded and a data area in which data information is recorded.

公开(公告)号：US5126963A

公开(公告)日：1992-06-30

申请号：US526141

申请日：1990-05-22

Applicant: Hisako Fukasawa

Inventor： Hisako Fukasawa

IPC: G06F7/487 ,  G06F5/01 ,  G06F7/00 ,  G06F7/52 ,  G06F7/527 ,  G06F7/76

CPC classification number: G06F7/4876 ,  G06F5/012 ,  G06F2207/3884

Abstract: The amount of shifting required for normalizing a result of floating-point type multiplication is screened to determine if it falls within a predetermined range. The result is directly normalized in the event that the amount of shifting falls within the range while if the amount falls outside the predetermined range, the result is subject to coarse shifting until it falls in the predetermined range and then is normalized.

Abstract translation: 筛选对浮点型乘法结果进行归一化所需的移位量，以确定其是否在预定范围内。 在移位量落在范围内的情况下，直接归一化结果，而如果该量落在预定范围之外，则结果将进行粗移位，直到它落在预定范围内，然后被归一化。

公开(公告)号：US5059942A

公开(公告)日：1991-10-22

申请号：US460649

申请日：1990-01-03

Applicant: James L. Burrows

Inventor： James L. Burrows

IPC: G06F7/02 ,  G06F7/76 ,  G06F9/30

CPC classification number: G06F7/764 ,  G06F7/02 ,  G06F9/30021

Abstract: A masked compare circuit for comparing a first N-bit dataword to a second N-bit dataword, the circuit including a decoder for receiving an M-bit mask code and generating an output signal identifying a bit position, K, derived from the M-bit mask code, M and K being positive integers; and a comparator module responsive to the decoder output signal for comparing the N-K+1 most significant bits of the first dataword to corresponding bits of the second dataword, the comparator module generating an output signal having a first value when all of the compared bits are the same and having a second value when any of the compared bits are different.

Abstract translation: 一种用于将第一N位数据字与第二N位数据字进行比较的屏蔽比较电路，该电路包括一个解码器，用于接收一个M位掩码码，并产生一个识别从位M位导出的比特位置K的输出信号， 位掩码码，M和K为正整数; 以及响应于所述解码器输出信号的比较器模块，用于将所述第一数据字的N-K + 1个最高有效位与所述第二数据字的对应位进行比较，所述比较器模块在所有所述比较位产生具有第一值的输出信号 是相同的，并且当任何比较的比特不同时具有第二值。