公开(公告)号：US20210159833A1

公开(公告)日：2021-05-27

申请号：US16948906

申请日：2020-10-05

Applicant: Microchip Technology Incorporated

Inventor： Jason Qian ,  Betty Wang

IPC: H02P25/024 ,  H02P21/14 ,  H02P21/22

Abstract: Described embodiments relate to motor control for synchronous motors, and more specifically, some embodiments relate to motor-current control for permanent-magnet synchronous motors. Embodiments of a current controller are described that include an adaptive controller configured to adapt to changing system dynamics of a PMSM. Embodiments of adaptive control techniques are described that involve estimating system parameters of a PMSM and adapting control actions to compensate for such estimated system parameters. Such adapted control actions may be expected to track an observed motor current to a desired motor current. Systems, methods and devices related to the above are also described.

公开(公告)号：US20210117109A1

公开(公告)日：2021-04-22

申请号：US17133115

申请日：2020-12-23

Applicant: Microchip Technology Incorporated

Inventor： Brian Marley ,  Richard E. Wahler

IPC: G06F3/06 ,  G06F1/10 ,  G06F21/85 ,  G06F13/16

Abstract: An apparatus includes an interface circuit and a monitor circuit communicatively coupled to the interface circuit. The monitor circuit is configured to identify a command issued to a memory communicatively coupled to the monitor circuit through the interface circuit, determine whether the command is authorized, and, based on a determination that the command is not authorized, cancel the command.

公开(公告)号：US10983931B2

公开(公告)日：2021-04-20

申请号：US15141823

申请日：2016-04-29

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris ,  Calum Wilkie ,  Jason Sachs ,  Andreas Reiter

IPC: G06F13/12 ,  G06F13/16 ,  G06F9/30 ,  G06F9/38 ,  G06F12/14 ,  G06F13/40

Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

公开(公告)号：US20210109886A1

公开(公告)日：2021-04-15

申请号：US16840143

申请日：2020-04-03

Applicant: Microchip Technology Incorporated

Inventor： Johan Vaarlid

IPC: G06F13/42 ,  G06F13/10

Abstract: Embodiments of an N-channel serial peripheral interface are described, and N-channel serial communication links comprising the same. Also described are methods of communication using N-channel serial communication interfaces and links.

公开(公告)号：US20210099016A1

公开(公告)日：2021-04-01

申请号：US16730264

申请日：2019-12-30

Applicant: Microchip Technology Incorporated

Inventor： Santosh Manjunath Bhandarkar ,  Alex Dumais

IPC: H02J50/12 ,  H02J50/80 ,  G01R19/25

Abstract: In a wireless power transfer system for supplying power to a wireless device, e.g., charging a battery, wireless power transmitter coil voltage is used in place of coil current for communication and power control reference. The transmitter coil voltage waveforms provide phase information, with reference to the pulse width modulation (PWM) waveforms, that can be used to demodulate digital packet communication from a wireless power receiver used to provide a voltage to a device. The DC voltage amplitude of the wireless power transmitter coil is used for controlling the power injected to the wireless power receiver coil, while the phase of the transmitter coil voltage PWM signal is used for demodulation of signal packets from the wireless power receiver to control the transmitter coil voltage and thereby wireless power transfer to the power receiver.

公开(公告)号：US10955961B2

公开(公告)日：2021-03-23

申请号：US16001689

申请日：2018-06-06

Applicant: Microchip Technology Incorporated

Inventor： Lowry DuRant Lewis

IPC: G06F3/041 ,  G06F3/0488 ,  G06F3/0484 ,  G06F1/16

Abstract: Embodiments described in this disclosure relate, generally, to a touch user interface (UI) that interacts with, and may be used to manipulate, a graphical user interface (GUI) of a display utility presented at a graphical overlay, and systems and methods for implementing the same. Some embodiments of the disclosure may be incorporated into display systems, including bezel-less display systems.

公开(公告)号：US20210058268A1

公开(公告)日：2021-02-25

申请号：US16588764

申请日：2019-09-30

Applicant: Microchip Technology Incorporated

Inventor： Jiachi Yu ,  Dixon Chen ,  Kevin Yang

IPC: H04L12/40 ,  H04B17/309 ,  H04L12/413

Abstract: Systems, device, and methods related to estimating a Signal to Noise Ratio (SNR) of a signal are disclosed. A method of estimating an SNR includes setting a threshold of a comparator of a physical layer device to a first value, applying a signal to the comparator, and determining a first bit error number of an output of the comparator with the threshold set at the first value. The method also includes setting the threshold of the comparator to a second value that is different from the first value, applying the signal to the comparator, and determining a second bit error number of the output of the comparator with the threshold set at the second value. The method further includes determining an SNR of the signal based on the first bit error number and the second bit error number.

公开(公告)号：US20210043560A1

公开(公告)日：2021-02-11

申请号：US16741921

申请日：2020-01-14

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00

Abstract: A process of forming a metal-insulator-metal (MIM) capacitor may be incorporated into a process of forming metal bond pads connected directly to a top metal interconnect layer (e.g., Cu MTOP). The MIM capacitor may include a dielectric layer formed between a bottom plate defined by the Cu MTOP and a top plate comprising an extension of, or connected directly to, a metal bond pad formed above the Cu MTOP. The process of forming the MIM capacitor may include etching an opening in a passivation layer formed over the Cu MTOP to expose a top surface of the Cu MTOP, forming a dielectric layer extending into the passivation layer opening and onto the exposed Cu MTOP surface, removing portions of the dielectric layer to define a capacitor dielectric, and depositing bond pad metal extending into the passivation layer opening and onto the capacitor dielectric, to define the MIM capacitor top plate.

公开(公告)号：US20210020568A1

公开(公告)日：2021-01-21

申请号：US16549635

申请日：2019-08-23

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/00 ,  H01L21/768

Abstract: In some embodiments, integrated inductors may be built using processes for forming interconnects of semiconductor devices without requiring additional process steps. Integrated inductor coils may be formed by, for example, shunting an overlying electrically conductive material, such as, for example, bond pad metals (e.g., aluminum and alloys thereof), to an underlying electrically conductive material, such as, for example, an uppermost layer of wiring formed using Damascene processes (e.g., utilizing copper and alloys thereof), without vias to interconnect the two materials. In some embodiments, integrated inductors formed utilizing such processes may have a symmetric spiral design.

公开(公告)号：US10897274B2

公开(公告)日：2021-01-19

申请号：US16174724

申请日：2018-10-30

Applicant: Microchip Technology Incorporated

Inventor： Vishal Sharma

IPC: H04B1/00 ,  H04W88/18 ,  H04W88/12 ,  H04W72/10 ,  G06F13/40 ,  G06F13/362

Abstract: A radio arbiter circuit is disclosed comprising a digital connection to a radio circuit, which comprises a transmitter, a receiver, and a radio frequency antenna; a first connection to a first network link controller, which comprises a first baseband processor and a first interface to a processor bus; a second connection to a second network link controller, which comprises a second baseband processor and a second interface to a processor bus; a multiplexer for coupling either the first network link controller or the second network link controller to the radio circuit via the digital connection; and a control input to the multiplexer for selecting which network link controller has control of the radio circuit.