公开(公告)号：US11362201B1

公开(公告)日：2022-06-14

申请号：US17120916

申请日：2020-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sarah McTaggart ,  Qizhi Liu ,  Vibhor Jain ,  Mark Levy ,  Paula Fisher ,  James R. Elliott

IPC: H01L29/737 ,  H01L29/66

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.

公开(公告)号：US20220165676A1

公开(公告)日：2022-05-26

申请号：US16953441

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Sunil K. Singh ,  Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  John J. Ellis-Monaghan ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/00

Abstract: The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure.

公开(公告)号：US11333558B2

公开(公告)日：2022-05-17

申请号：US16181972

申请日：2018-11-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik ,  Steven M. Shank

IPC: G01K1/02 ,  H01L45/00 ,  G01K7/22 ,  H01L27/24 ,  H01L23/522 ,  G01K7/16 ,  H01L27/00 ,  H01L23/482 ,  H01L27/06

Abstract: One device disclosed herein includes, among other things, a substrate, a first resistor comprising a first phase transition material formed above the substrate, the first phase transition material exhibiting a first dielectric phase for temperatures less than a first phase transition temperature and a first semiconductor phase for temperatures greater than the first phase transition temperature, and logic to detect a transition of the first resistor to the first semiconductor phase.

公开(公告)号：US11322497B1

公开(公告)日：2022-05-03

申请号：US17172539

申请日：2021-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yves T. Ngu ,  Ephrem G. Gebreselasie ,  Vibhor Jain ,  Johnatan A. Kantarovsky

IPC: H01L27/102 ,  H01L23/525 ,  H01L23/62

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.

公开(公告)号：US20220062896A1

公开(公告)日：2022-03-03

申请号：US17006050

申请日：2020-08-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Vibhor Jain ,  Anthony Stamper ,  John Pekarik ,  John Ellis-Monaghan ,  Ramsey Hazbun

IPC: B01L3/00 ,  G01N21/05 ,  G01N21/85

Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a channel that is at least partially defined by at least a portion of the semiconductor substrate, an input fluid reservoir and an output fluid reservoir, wherein the channel is in fluid communication with the input fluid reservoir and the output fluid reservoir. In this example, the device further includes a first radiation source operatively coupled to the substrate, wherein the first radiation source is adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent the channel.

公开(公告)号：US11177347B2

公开(公告)日：2021-11-16

申请号：US16830783

申请日：2020-03-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.

公开(公告)号：US20210336005A1

公开(公告)日：2021-10-28

申请号：US16855236

申请日：2020-04-22

Applicant: GLOBALFOUNDRIES U.S. Inc

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/08 ,  H01L29/78

Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.

公开(公告)号：US11158722B2

公开(公告)日：2021-10-26

申请号：US16730371

申请日：2019-12-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Steven M. Shank ,  John J. Pekarik ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/15 ,  H01L29/16 ,  H01L29/267 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with an oxygen lattice structure and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the substrate; at least one oxygen film separating the sub-collector region and the collector region; an emitter region adjacent to the collector region; and a base region adjacent to the emitter region.

公开(公告)号：US11127831B2

公开(公告)日：2021-09-21

申请号：US16788914

申请日：2020-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik ,  Judson R. Holt

IPC: H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/45 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.

公开(公告)号：US11063139B2

公开(公告)日：2021-07-13

申请号：US16748055

申请日：2020-01-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Judson Holt

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A collector layer includes an inclined side surface, and a dielectric layer is positioned in a lateral direction adjacent to the inclined side surface of the collector layer. An intrinsic base is disposed over the collector layer, and an emitter is disposed over the intrinsic base. An airgap is positioned between the dielectric layer and the inclined side surface of the collector layer in the lateral direction, and an extrinsic base is positioned in the lateral direction adjacent to the intrinsic base. The extrinsic base is positioned over the airgap.