公开(公告)号：US07224182B1

公开(公告)日：2007-05-29

申请号：US11082221

申请日：2005-03-15

申请人： Brad Hutchings ,  Herman Schmit ,  Steven Teig

发明人： Brad Hutchings ,  Herman Schmit ,  Steven Teig

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748

摘要： Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs, (2) a set of outputs for selectively connecting to the set of inputs, and (3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner. At least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.

摘要翻译： 本发明的一些实施例提供了可配置的集成电路（“IC”）。 该IC包括用于接收配置数据并且可配置地基于配置数据执行一组操作的多个可配置逻辑电路。 它还包括几个混合电路。 每个特定的混合电路具有：（1）一组输入，（2）用于选择性地连接到该组输入的一组输出，以及（3）一组选择线，用于接收引导混合电路连接的选择信号 将输入以特定方式设置为输出集。 至少一个选择信号用于可控地接收配置数据，并且至少一个选择线用于可控地接收由可配置逻辑电路产生的信号。

公开(公告)号：US07193432B1

公开(公告)日：2007-03-20

申请号：US10882579

申请日：2004-06-30

申请人： Herman Schmit ,  Steven Teig

发明人： Herman Schmit ,  Steven Teig

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： H03K19/17756 ,  H03K19/17776 ,  H03K19/17796

摘要： Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set. The second circuit communicatively couples to the first logic circuit. The second circuit is for supplying configuration data sets to the first logic circuit. The second circuit has a first set of input terminals. The integrated circuit also has a second set of input terminals for carrying data. Several the second set of input terminals overlap several of the first set of input terminals. The IC also has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set.

摘要翻译： 本发明的一些实施例提供了一种可配置的集成电路（IC）。 IC包括第一和第二电路。 第一电路是用于接收配置数据集并且当接收第二配置数据集时接收第一配置数据集和第二功能时执行至少第一功能的逻辑电路。 第二电路通信耦合到第一逻辑电路。 第二电路用于将配置数据组提供给第一逻辑电路。 第二电路具有第一组输入端子。 集成电路还具有用于承载数据的第二组输入端子。 几个第二组输入端与第一组输入端重叠。 IC还具有一组通孔，其中每个通孔将第一组中的输入端与第二组中的输入端连接。

公开(公告)号：US07157933B1

公开(公告)日：2007-01-02

申请号：US10882583

申请日：2004-06-30

申请人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

发明人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17776

摘要： Some embodiments of the invention provide a first configurable integrated circuit (IC) that has a first configurable IC design. The first configurable IC implements a second IC design that is specified for a second IC that is to operate a particular design rate. The first configurable IC includes several configurable logic circuits. Each configurable logic circuit can configurably perform a set of functions. The IC also includes several configurable interconnect circuits that configurably couple the logic circuits. At least several configurable circuits can reconfigure faster than the particular design rate.

摘要翻译： 本发明的一些实施例提供了具有第一可配置IC设计的第一可配置集成电路（IC）。 第一个可配置IC实现了第二个IC设计，该第二个IC设计指定用于操作特定设计速率的第二个IC。 第一个可配置的IC包括几个可配置的逻辑电路。 每个可配置的逻辑电路可配置地执行一组功能。 IC还包括可配置地耦合逻辑电路的几个可配置互连电路。 至少几个可配置电路可以比特定设计速率重新配置更快。

公开(公告)号：US07126373B1

公开(公告)日：2006-10-24

申请号：US10882839

申请日：2004-06-30

申请人： Herman Schmit ,  Steven Teig

发明人： Herman Schmit ,  Steven Teig

IPC分类号： H03K19/173

CPC分类号： H03K19/17756 ,  H03K19/17728

摘要： Some embodiments of the invention provide a configurable logic circuit. The logic circuits has inputs for receiving input data. It also has a first connecting circuit for receiving configuration data and at least a portion of the input data. Based at least partially on the received portion of the input data, the first connecting circuit selects configuration data sub-sets. The logic circuit also includes a second core-logic circuit for receiving configuration data sub-sets from the first connecting circuit and for providing the output data. At least two configuration data sub-sets configure the configurable logic circuit to perform at least two different functions on the input data to produce output data.

摘要翻译： 本发明的一些实施例提供了一种可配置的逻辑电路。 逻辑电路具有用于接收输入数据的输入。 它还具有用于接收配置数据和至少一部分输入数据的第一连接电路。 至少部分地基于输入数据的接收部分，第一连接电路选择配置数据子集。 逻辑电路还包括用于从第一连接电路接收配置数据子集并用于提供输出数据的第二核心逻辑电路。 至少两个配置数据子集配置可配置逻辑电路以在输入数据上执行至少两个不同的功能以产生输出数据。

公开(公告)号：US07109752B1

公开(公告)日：2006-09-19

申请号：US10883276

申请日：2004-06-30

申请人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

发明人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17744 ,  H03K19/17776

摘要： Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable IC has an array of configurable circuits. The array includes several configurable logic and interconnect circuits. Each configurable logic circuit can configurably perform a set of functions. The configurable interconnect circuits can configurably couple the logic circuits. At least several of the configurable circuits can be reconfigured faster than the first rate.

公开(公告)号：US09148151B2

公开(公告)日：2015-09-29

申请号：US13549405

申请日：2012-07-13

申请人： Steven Teig ,  Christopher D. Ebeling ,  Martin Voogel ,  Andrew Caldwell

发明人： Steven Teig ,  Christopher D. Ebeling ,  Martin Voogel ,  Andrew Caldwell

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1736 ,  H03K19/17744

摘要： A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate.

摘要翻译： 提供了一个低功率子循环可重新配置的管道。 低功率可重新配置的管道是一种时钟存储元件，当执行不需要子周期速率的低通量操作时，可以消耗较少的功耗。 低功率管道包括第一可配置路由多路复用器，其可重新配置以以第一时钟速率选择多个输入中的一个。 低功率管道还包括用于以第一时钟速率存储来自可配置路由多路复用器的输出数据的存储元件阵列。 存储元件阵列中的每个存储元件以比第一时钟速率慢的第二时钟速率工作。 每个存储元件接收以第二时钟速率工作的时钟的不同相位。 低功率管道还包括可配置的第二可配置路由多路复用器，以便以第一时钟速率从存储元件阵列中进行选择。

公开(公告)号：US08863067B1

公开(公告)日：2014-10-14

申请号：US12027260

申请日：2008-02-06

申请人： Andrew Caldwell ,  Steven Teig

发明人： Andrew Caldwell ,  Steven Teig

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031

摘要： Some embodiments provide a method of designing an integrated circuit (IC). The design is expressed as a graph that includes several nodes that represent several IC components. The nodes include a first set of nodes that represent a set of clocked elements. The method creates a second set of nodes by removing all nodes in the first set from the nodes that represent the IC components. The method identifies a set of edges that connect two nodes in the second set without encompassing a third node in the second set. The method assigns an event time to each node in the second set. The method assigns a cost function based on the event times of the nodes connected by each edge and the number of nodes in the first set encompassed by each edge. The method optimizes the cost function and places the components based on the cost function optimization.

摘要翻译： 一些实施例提供了一种设计集成电路（IC）的方法。 该设计表示为包括代表几个IC组件的几个节点的图形。 节点包括表示一组时钟元件的第一组节点。 该方法通过从代表IC组件的节点中删除第一组中的所有节点来创建第二组节点。 该方法识别连接第二组中的两个节点而不包含第二组中的第三节点的一组边。 该方法为第二组中的每个节点分配一个事件时间。 该方法基于由每个边缘连接的节点的事件时间和由每个边缘包围的第一组中的节点的数量来分配成本函数。 该方法优化了成本函数，并根据成本函数优化放置了组件。

公开(公告)号：US08429579B2

公开(公告)日：2013-04-23

申请号：US13291087

申请日：2011-11-07

申请人： Brad Hutchings ,  Andrew Caldwell ,  Steven Teig

发明人： Brad Hutchings ,  Andrew Caldwell ,  Steven Teig

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5045 ,  G06F2217/84

摘要： Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

摘要翻译： 一些实施例提供了在可配置集成电路（IC）中监视用户设计的实现的方法。 该方法接收IC的用户设计，并优化用户设计以产生第二IC设计。 优化导致消除电路元件。 该方法定义了可配置IC的第二个IC设计，并为消除的电路元件生成输出数据，以便监视用户设计。

公开(公告)号：US20110154279A1

公开(公告)日：2011-06-23

申请号：US12994453

申请日：2009-05-22

申请人： Andrew Caldwell ,  Steven Teig

发明人： Andrew Caldwell ,  Steven Teig

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.

摘要翻译： 描述了用于放置在电路设计的逻辑表示（即，网表中）的抽象决策模块原语。 决策模块原语接收网表的给定功能或段的输入替代解决方案。 替代解决方案包括功能等同，但在网表的功能或段的结构上不同的实现。 所述决策模块基元可选择在连接到所述网表之一的输入之间，以基于约束信息为所述网表提供完整的功能定义。 当在设计过程的各个阶段确定附加约束信息时，可以更新决策模块的所选择的输入。 此外，当识别出额外的约束信息时，可以向决策模块的输入添加和/或从其中删除网表的给定功能或段的替代解决方案。

公开(公告)号：US20090007027A1

公开(公告)日：2009-01-01

申请号：US11769680

申请日：2007-06-27

申请人： Brad Hutchings ,  Andrew Caldwell ,  Steven Teig

发明人： Brad Hutchings ,  Andrew Caldwell ,  Steven Teig

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5045 ,  G06F2217/84

摘要： Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit elements(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

摘要翻译： 一些实施例提供了在可配置集成电路（IC）中监视用户设计的实现的方法。 该方法接收IC的用户设计，并优化用户设计以产生第二IC设计。 优化导致消除电路元件。 该方法定义了可配置IC的第二个IC设计，并为消除的电路元件生成输出数据，以便监视用户设计。