公开(公告)号：US20210111156A1

公开(公告)日：2021-04-15

申请号：US17129221

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

公开(公告)号：US10969576B2

公开(公告)日：2021-04-06

申请号：US16072164

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Sasha N. Oster ,  Shawna M. Liff ,  Johanna M. Swan ,  Thomas L. Sounart ,  Baris Bicen ,  Valluri R. Rao

IPC: G02B26/10 ,  G02B26/08 ,  G02B1/14

Abstract: Disclosed herein are maskless imaging tools and display systems that include piezoelectrically actuated mirrors and methods of forming such devices. The maskless imaging tool may include a light source. Additionally, the tool may include one or more piezoelectrically actuated mirrors for receiving light from the light source. The piezoelectrically actuated mirrors are actuatable about one or more axes to reflect the light from the light source to a workpiece positioned to receive light from the piezoelectrically actuated mirror. Disclosed herein is a maskless imaging tool that is a laser direct imaging lithography (LDIL) tool. The maskless imaging tool may also be a via-drill tool. Disclosed herein is also a piezoelectrically actuated mirror used in a projection system. For example, the projection system may be integrated into a pair of glasses.

公开(公告)号：US10816733B2

公开(公告)日：2020-10-27

申请号：US16072240

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Johanna M. Swan ,  Feras Eid ,  Thomas L. Sounart ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Baris Bicen ,  Valluri R. Rao

IPC: G02B6/35 ,  H04Q11/00 ,  G02B26/08 ,  H04B10/25

Abstract: Embodiments of the invention include an optical routing device that includes an organic substrate. According to an embodiment, an array of cavities are formed into the organic substrate and an array of piezoelectrically actuated mirrors may be anchored to the organic substrate with each piezoelectrically actuated mirror extending over a cavity. In order to properly rout incoming optical signals, the optical routing device may also include a routing die mounted on the organic substrate. The routing die may be electrically coupled to each of the piezoelectrically actuated mirrors and is able to generated a voltage across the first and second electrodes of each piezoelectrically actuated mirror. Additionally, a photodetector may be electrically coupled to the routing die. According to an embodiment, an array of fiber optic cables may be optically coupled with one of the piezoelectrically actuated mirrors and optically coupled with the photodetector.

公开(公告)号：US20200227384A1

公开(公告)日：2020-07-16

申请号：US16650656

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/544

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US10658566B2

公开(公告)日：2020-05-19

申请号：US16072166

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Feras Eid ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Baris Bicen ,  Thomas L. Sounart ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Valluri R. Rao

IPC: G02B26/00 ,  H01L41/09 ,  H01L27/32 ,  H05B45/00 ,  F21S10/02 ,  G02F1/01 ,  H01L41/22 ,  H01L51/00 ,  G06F3/041

Abstract: Embodiments of the invention include piezoelectrically driven switches that are used for modifying a background color or light source color in display systems, and methods of forming such devices. In an embodiment, a piezoelectrically actuated switch for modulating a background color in a display may include a photonic crystal that has a plurality of blinds oriented substantially perpendicular to a surface of the display. In an embodiment, the blinds include a black surface and a white surface. The switch may also include an anchor spaced away from an edge of the photonic crystal and a piezoelectric actuator formed on the surface of the anchor and a surface of the photonic crystal. Some embodiments may include a photonic crystal that is a multi-layer polymeric structure or a polymer chain with a plurality of nanoparticles spaced at regular intervals on the polymer chain.

公开(公告)号：US20200098621A1

公开(公告)日：2020-03-26

申请号：US16140398

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Kaladhar Radhakrishnan ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L21/768

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

公开(公告)号：US20200091128A1

公开(公告)日：2020-03-19

申请号：US16161578

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Shawna M. Liff ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/532 ,  H01L23/66 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.

公开(公告)号：US20200067816A1

公开(公告)日：2020-02-27

申请号：US16106926

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Tejpal Singh ,  Shawna M. Liff ,  Gerald S. Pasdast ,  Johanna M. Swan

IPC: H04L12/733 ,  H04L12/933 ,  G06F12/0842 ,  H04L29/06

Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.

公开(公告)号：US20190312001A1

公开(公告)日：2019-10-10

申请号：US16464930

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Veronica A. Strong ,  Sasha N. Oster ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A system for packaging integrated circuits includes an integrated circuit having one or more integrated circuit terminals. The system for packaging integrated circuits also includes a substrate having one or more substrate terminals. The system for packaging integrated circuits further includes an electrically conductive adhesive in communication with the integrated circuit terminals and the substrate terminals. The electrically conductive adhesive establishes an electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals. The electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals are enclosed in a dielectric. The system for packaging integrated circuits includes a second adhesive in communication with the integrated circuit and the substrate, wherein the second adhesive couples the integrated circuit and substrate together.

公开(公告)号：US10256205B2

公开(公告)日：2019-04-09

申请号：US15812754

申请日：2017-11-14

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Jimin Yao ,  Shawna M. Liff

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.