公开(公告)号：US20210134825A1

公开(公告)日：2021-05-06

申请号：US17145131

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L23/532 ,  H01L21/28

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US10943915B1

公开(公告)日：2021-03-09

申请号：US16552257

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Albert Fayrushin ,  Haitao Liu ,  Kirk D. Prall

IPC: H01L27/11553 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.

公开(公告)号：US10937904B2

公开(公告)日：2021-03-02

申请号：US15890530

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11597 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/1159 ,  H01L29/66

Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

公开(公告)号：US20210057441A1

公开(公告)日：2021-02-25

申请号：US16550252

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US20210050443A1

公开(公告)日：2021-02-18

申请号：US16542078

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L29/267 ,  H01L29/45 ,  H01L29/08 ,  H01L29/10 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source; drain region.

公开(公告)号：US20210027839A1

公开(公告)日：2021-01-28

申请号：US17067550

申请日：2020-10-09

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US10903223B2

公开(公告)日：2021-01-26

申请号：US16248248

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/115 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L23/532 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US10818357B2

公开(公告)日：2020-10-27

申请号：US16518687

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US20200286893A1

公开(公告)日：2020-09-10

申请号：US16291597

申请日：2019-03-04

Applicant: Micron Technology, Inc.

Inventor： Arzum F. Simsek-Ege ,  Kamal M. Karda ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/285

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.

公开(公告)号：US20190252553A1

公开(公告)日：2019-08-15

申请号：US16132879

申请日：2018-09-17

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Yunfei Gao ,  Kamal M. Karda ,  Deepak Chandra Pandey ,  Sanh D. Tang ,  Litao Yang

IPC: H01L29/786 ,  H01L29/78 ,  H01L27/088

Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.