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公开(公告)号:US20200152267A1
公开(公告)日:2020-05-14
申请号:US16744643
申请日:2020-01-16
Applicant: Micron Technology, Inc.
Inventor: Marco Dallabora , Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri
Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.
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公开(公告)号:US10592427B2
公开(公告)日:2020-03-17
申请号:US16052921
申请日:2018-08-02
Applicant: Micron Technology, Inc.
Inventor: Daniele Balluchi , Dionisio Minopoli
IPC: G06F12/1009
Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.
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公开(公告)号:US10573383B2
公开(公告)日:2020-02-25
申请号:US16124222
申请日:2018-09-07
Applicant: Micron Technology, Inc.
Inventor: Marco Dallabora , Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri
Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.
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公开(公告)号:US20200050554A1
公开(公告)日:2020-02-13
申请号:US16655769
申请日:2019-10-17
Applicant: Micron Technology, Inc.
Inventor: Daniele Balluchi , Dionisio Minopoli
IPC: G06F12/1009
Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.
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公开(公告)号:US10430085B2
公开(公告)日:2019-10-01
申请号:US15345783
申请日:2016-11-08
Applicant: Micron Technology, Inc.
Inventor: Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora
IPC: G06F3/06 , G06F12/1009 , G06F11/10 , G11C16/34
Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.
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公开(公告)号:US20190294547A1
公开(公告)日:2019-09-26
申请号:US15927530
申请日:2018-03-21
Applicant: Micron Technology, Inc.
Inventor: Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora , Roberto Izzi , Paolo Amato , Daniele Balluchi , Luca Porzio
IPC: G06F12/0862 , G06F12/10
Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
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公开(公告)号:US20190294356A1
公开(公告)日:2019-09-26
申请号:US15927339
申请日:2018-03-21
Applicant: Micron Technology, Inc.
Inventor: Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora , Roberto Izzi , Paolo Amato , Daniele Balluchi , Luca Porzio
IPC: G06F3/06
Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.
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公开(公告)号:US20190102112A1
公开(公告)日:2019-04-04
申请号:US16207453
申请日:2018-12-03
Applicant: Micron Technology, Inc.
Inventor: Victor Y. Tsai , Danilo Caraccio , Daniele Balluchi , Neal A. Galbo , Robert Warren
IPC: G06F3/06
Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
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公开(公告)号:US20180336146A1
公开(公告)日:2018-11-22
申请号:US15815209
申请日:2017-11-16
Applicant: Micron Technology, Inc.
Inventor: Greg Blodgett , Daniele Balluchi , Danilo Caraccio , Graziano Mirichigni
Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.
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公开(公告)号:US20180129423A1
公开(公告)日:2018-05-10
申请号:US15345783
申请日:2016-11-08
Applicant: Micron Technology, Inc.
Inventor: Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora
IPC: G06F3/06 , G06F12/1009 , G06F11/10
CPC classification number: G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0634 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/0683 , G06F11/1048 , G06F11/1076 , G06F12/1009 , G06F2212/65 , G11C16/3495
Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.
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