公开(公告)号：US20190027200A1

公开(公告)日：2019-01-24

申请号：US15984914

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: G11C11/00 ,  H01L27/108 ,  H01L27/24 ,  H01L23/528 ,  H01L49/02 ,  H01L45/00

CPC classification number: G11C11/005 ,  G11C5/025 ,  G11C14/0045 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10897 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

公开(公告)号：US10037996B2

公开(公告)日：2018-07-31

申请号：US15646380

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/00 ,  H01L27/108 ,  H01L21/3205 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06 ,  H01L21/266 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L27/10814 ,  H01L21/266 ,  H01L21/3205 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/76224 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53261 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649

Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a first contact structure on a sidewall of the bit line structure, a second contact structure on the bit line structure and spaced apart from the first contact structure across the bit line structure, and an insulation pattern between the bit line structure and the first contact structure. The second contact structure covers at least a portion of a top surface of the bit line structure. The insulation pattern comprises a protrusion that protrudes from a sidewall of the insulation pattern that immediately adjacent to the bit line structure. The protrusion protrudes in a first direction parallel to a top surface of the substrate.

公开(公告)号：US09831172B2

公开(公告)日：2017-11-28

申请号：US14971402

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Jemin Park ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L21/02 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10897 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.

公开(公告)号：US20170323893A1

公开(公告)日：2017-11-09

申请号：US15584342

申请日：2017-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US09508649B2

公开(公告)日：2016-11-29

申请号：US14991020

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L29/78 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.

Abstract translation: 提供半导体器件。 半导体器件可以包括设置在半导体衬底上的第一互连结构和第二互连结构。 接触结构可以设置在第一和第二互连结构之间。 第一下部空气间隔件可以设置在第一互连结构和接触结构之间。 第二下部空气间隔件可以设置在第二互连结构和接触结构之间以与第一下部空气间隔件间隔开。 上空气隔离件可以设置在接触结构的侧表面上，以连接到第一和第二互连结构。

公开(公告)号：US20160211215A1

公开(公告)日：2016-07-21

申请号：US14991020

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L29/423 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.

Abstract translation: 提供半导体器件。 半导体器件可以包括设置在半导体衬底上的第一互连结构和第二互连结构。 接触结构可以设置在第一和第二互连结构之间。 第一下部空气间隔件可以设置在第一互连结构和接触结构之间。 第二下部空气间隔件可以设置在第二互连结构和接触结构之间以与第一下部空气间隔件间隔开。 上空气隔离件可以设置在接触结构的侧表面上，以连接到第一和第二互连结构。

公开(公告)号：US20140159148A1

公开(公告)日：2014-06-12

申请号：US14097937

申请日：2013-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Woo Chung ,  Jiyoung Kim ,  Yoosang Hwang

IPC: H01L29/78

CPC classification number: H01L27/10814 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894

Abstract: A method of manufacturing a semiconductor device includes forming device isolation layer in a substrate to define active regions of which each has first regions and a second region between the first regions, forming a first trench and a pair of second trenches in the substrate, and forming gates in the second trenches, respectively. The first trench extends in a first direction and crosses the active regions and the device isolation layer. The second trenches are connected to a bottom of the first trench and extend in the first direction at both sides of the second regions.

Abstract translation: 一种制造半导体器件的方法包括在衬底中形成器件隔离层，以限定其中各具有第一区域的有源区和在第一区之间的第二区，在衬底中形成第一沟槽和一对第二沟槽， 分别在第二壕沟的大门。 第一沟槽沿第一方向延伸并与有源区和器件隔离层交叉。 第二沟槽连接到第一沟槽的底部并且在第二区域的两侧沿第一方向延伸。