公开(公告)号：US20210233919A1

公开(公告)日：2021-07-29

申请号：US17230191

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Pai Chi Chou

IPC: H01L27/1159 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a first doped region and a second doped region within a substrate. A ferroelectric material is arranged over the substrate and laterally between the first doped region and the second doped region. A conductive electrode is over the ferroelectric material and between sidewalls of the ferroelectric material. One or more sidewall spacers are arranged along opposing sides of the ferroelectric material. A dielectric layer continuously and laterally extends from directly below the one or more sidewall spacers to directly below the ferroelectric material.

公开(公告)号：US10971590B2

公开(公告)日：2021-04-06

申请号：US16661108

申请日：2019-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having interior surfaces that define a trench within an upper surface of the substrate. One or more dielectric materials are disposed within the trench. A source region disposed within the substrate and a drain region is disposed within of the substrate and separated from the source region along a first direction. A gate structure is over the upper surface of the substrate between the source region and the drain region. The upper surface of the substrate has a first width directly below the gate structure that is larger than a second width of the upper surface of the substrate within the source region or the drain region. The first width and the second width are measured along a second direction that is perpendicular to the first direction.

公开(公告)号：US20210074712A1

公开(公告)日：2021-03-11

申请号：US16950144

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US10861951B2

公开(公告)日：2020-12-08

申请号：US16550497

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming an isolation structure within an upper surface of a substrate. The isolation structure surrounds a continuous region of the substrate defining a source area, a drain area, and a channel area. A gate structure is formed over the channel area. An implantation process is performed to form a source region within the source area and a drain region within the drain area. The channel area is arranged between the source region and the drain region along a first direction and extends past the source region and the drain region along a second direction that is perpendicular to the first direction. The first direction and the second direction are parallel to the upper surface of the substrate.

公开(公告)号：US20200321337A1

公开(公告)日：2020-10-08

申请号：US16906031

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an isolation structure within a substrate. The isolation structure surrounds a device region of the substrate. A sacrificial gate material is formed over the isolation structure and the device region of the substrate. A part of the sacrificial gate material is removed and a second metal is deposited where the part of the sacrificial gate material was removed. A remainder of the sacrificial gate material is subsequently removed and a first metal is deposited where the remainder of the sacrificial gate material was removed. The first metal is different than the second metal.

公开(公告)号：US20200295001A1

公开(公告)日：2020-09-17

申请号：US16887138

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench within the substrate. The trench surrounds the source region and the drain region. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate metal having a first sidewall and a second gate metal having a first outer sidewall that contacts the first sidewall directly over the upper surface of the substrate.

公开(公告)号：US20200258892A1

公开(公告)日：2020-08-13

申请号：US16860234

申请日：2020-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC: H01L27/11 ,  G06F30/398 ,  G06F30/39 ,  G11C29/12 ,  G11C29/04 ,  G11C29/08 ,  G11C29/50 ,  H01L23/528

Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

公开(公告)号：US10741555B2

公开(公告)日：2020-08-11

申请号：US16574205

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/51

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a source region and a drain region. The drain region is separated from the source region by a channel region. An isolation structure surrounds the source region, the drain region, and the channel region. A gate structure is over the channel region. The gate structure includes a first gate electrode region having one or more first materials and a second gate electrode region having one or more second materials that are different than the one or more first materials. The second gate electrode region continuously extends between a first outermost sidewall directly over the isolation structure and a second outermost sidewall directly over the channel region.

公开(公告)号：US10672778B2

公开(公告)日：2020-06-02

申请号：US15725000

申请日：2017-10-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin Liu ,  Wei Cheng Wu ,  Yi Hsien Lu ,  Yu-Hsiung Wang ,  Juo-Li Yang

IPC: H01L29/788 ,  H01L27/11546 ,  H01L27/088 ,  H01L21/28 ,  H01L27/105 ,  H01L27/11 ,  G11C16/12 ,  G11C16/04 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11548 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20200098777A1

公开(公告)日：2020-03-26

申请号：US16695475

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11575 ,  H01L21/762 ,  H01L27/11573 ,  H01L21/76 ,  H01L29/06

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed within a substrate and a plurality of memory devices disposed within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a protrusion extending outward from an upper surface of the first isolation structure. A logic wall is arranged on the protrusion and surrounds the plurality of memory devices.